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dc.contributor.authorNavarro Muñoz, Antoni
dc.contributor.authorLorenzon, Arthur F.
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorBeltran Querol, Vicenç
dc.contributor.otherUniversitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2021-10-15T09:15:41Z
dc.date.available2021-10-15T09:15:41Z
dc.date.issued2021
dc.identifier.citationNavarro, A. [et al.]. Combining dynamic concurrency throttling with voltage and frequency scaling on task-based programming models. A: International Conference on Parallel Processing. "The 50th International Conference on Parallel Processing: August 9-12, 2021, hosted virtually from Chicago, Illinois, USA: main conference proceedings". New York: Association for Computing Machinery (ACM), 2021, p. 1-11. ISBN 978-1-4503-9068-2. DOI 10.1145/3472456.3472471.
dc.identifier.isbn978-1-4503-9068-2
dc.identifier.urihttp://hdl.handle.net/2117/353698
dc.description.abstractBeing on the verge of exascale performance has shifted the prioritization of performance in applications to the inclusion of power-performance efficiency as a primary objective in the High Performance Computing (HPC) community. Simultaneously, this has surfaced hardware and software efforts that employ techniques such as dynamic voltage and frequency scaling (DVFS) for core and uncore units or dynamic concurrency throttling (DCT) to exploit hardware resources efficiently, by saving energy while maintaining performance. These techniques are complementary, so they can be used together. However, employing them is not a straightforward task, as they have to be adjusted based on the workload, and it is even more complex to combine them properly. Thus, these techniques should be applied transparently by a runtime system, without relying on application developers. In this paper, we extend a task-based runtime system with an infrastructure that categorizes workloads based on their computational profile – memory-bounded, compute-bounded, or balanced. This categorization is done in an on-line manner and with a negligible overhead. With this additional information, we enhance the CPU-manager and scheduler of OmpSs-2, a task-based parallel programming model, to automatically combine DVFS and DCT techniques based on workloads. Moreover, we show that our heuristics transparently improve energy efficiency on average by 15% with no significant performance loss and either equal or surpass the energy efficiency of the best static configuration available.
dc.description.sponsorshipThis research has received funding from the European Union’s Horizon 2020/EuroHPC research and innovation programme under grant agreement N.955606 (DEEP-SEA), and is supported by the Spanish State Research Agency - Ministry of Science and Innovation (contract PID2019-107255GB), and by the Generalitat de Catalunya (2017-SGR-1414). This work was also supported by Project HPC- EUROPA3, with the support of the EC Research Innovation Action under the H2020 Programme.
dc.format.extent11 p.
dc.language.isoeng
dc.publisherAssociation for Computing Machinery (ACM)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.lcshHigh performance computing -- Energy conservation
dc.subject.otherModeling and prediction
dc.subject.otherEnergy-awareness
dc.subject.otherPower-performance
dc.subject.otherDVFS
dc.subject.otherDCT
dc.subject.otherOmpSs-2
dc.subject.otherOpenMP
dc.subject.otherUncore
dc.subject.otherScheduling
dc.subject.otherOptimization
dc.titleCombining dynamic concurrency throttling with voltage and frequency scaling on task-based programming models
dc.typeConference report
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.subject.lemacCàlcul intensiu (Informàtica) -- Estalvi d'energia
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1145/3472456.3472471
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://dl.acm.org/doi/10.1145/3472456.3472471
dc.rights.accessOpen Access
local.identifier.drac32106539
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/AGAUR/2017 SGR 1414
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/955606/EU/DEEP – SOFTWARE FOR EXASCALE ARCHITECTURES/DEEP-SEA
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/730897/EU/Transnational Access Programme for a Pan-European Network of HPC Research Infrastructures and Laboratories for scientific computing/HPC-EUROPA3
local.citation.authorNavarro, A.; Lorenzon, A.; Ayguadé, E.; Beltran, V.
local.citation.contributorInternational Conference on Parallel Processing
local.citation.pubplaceNew York
local.citation.publicationNameThe 50th International Conference on Parallel Processing: August 9-12, 2021, hosted virtually from Chicago, Illinois, USA: main conference proceedings
local.citation.startingPage1
local.citation.endingPage11


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