dc.contributor.author | Navarro Muñoz, Antoni |
dc.contributor.author | Lorenzon, Arthur F. |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.author | Beltran Querol, Vicenç |
dc.contributor.other | Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Barcelona Supercomputing Center |
dc.date.accessioned | 2021-10-15T09:15:41Z |
dc.date.available | 2021-10-15T09:15:41Z |
dc.date.issued | 2021 |
dc.identifier.citation | Navarro, A. [et al.]. Combining dynamic concurrency throttling with voltage and frequency scaling on task-based programming models. A: International Conference on Parallel Processing. "The 50th International Conference on Parallel Processing: August 9-12, 2021, hosted virtually from Chicago, Illinois, USA: main conference proceedings". New York: Association for Computing Machinery (ACM), 2021, p. 1-11. ISBN 978-1-4503-9068-2. DOI 10.1145/3472456.3472471. |
dc.identifier.isbn | 978-1-4503-9068-2 |
dc.identifier.uri | http://hdl.handle.net/2117/353698 |
dc.description.abstract | Being on the verge of exascale performance has shifted the prioritization of performance in applications to the inclusion of power-performance efficiency as a primary objective in the High Performance Computing (HPC) community. Simultaneously, this has surfaced hardware and software efforts that employ techniques such as dynamic voltage and frequency scaling (DVFS) for core and uncore units or dynamic concurrency throttling (DCT) to exploit hardware resources efficiently, by saving energy while maintaining performance. These techniques are complementary, so they can be used together. However, employing them is not a straightforward task, as they have to be adjusted based on the workload, and it is even more complex to combine them properly. Thus, these techniques should be applied transparently by a runtime system, without relying on application developers. In this paper, we extend a task-based runtime system with an infrastructure that categorizes workloads based on their computational profile – memory-bounded, compute-bounded, or balanced. This categorization is done in an on-line manner and with a negligible overhead. With this additional information, we enhance the CPU-manager and scheduler of OmpSs-2, a task-based parallel programming model, to automatically combine DVFS and DCT techniques based on workloads. Moreover, we show that our heuristics transparently improve energy efficiency on average by 15% with no significant performance loss and either equal or surpass the energy efficiency of the best static configuration available. |
dc.description.sponsorship | This research has received funding from the European Union’s Horizon 2020/EuroHPC research and innovation programme under grant agreement N.955606 (DEEP-SEA), and is supported by the Spanish State Research Agency - Ministry of Science and Innovation (contract PID2019-107255GB), and by the Generalitat de Catalunya (2017-SGR-1414). This work was also supported by Project HPC- EUROPA3, with the support of the EC Research Innovation Action under the H2020 Programme. |
dc.format.extent | 11 p. |
dc.language.iso | eng |
dc.publisher | Association for Computing Machinery (ACM) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
dc.subject.lcsh | Parallel processing (Electronic computers) |
dc.subject.lcsh | High performance computing -- Energy conservation |
dc.subject.other | Modeling and prediction |
dc.subject.other | Energy-awareness |
dc.subject.other | Power-performance |
dc.subject.other | DVFS |
dc.subject.other | DCT |
dc.subject.other | OmpSs-2 |
dc.subject.other | OpenMP |
dc.subject.other | Uncore |
dc.subject.other | Scheduling |
dc.subject.other | Optimization |
dc.title | Combining dynamic concurrency throttling with voltage and frequency scaling on task-based programming models |
dc.type | Conference report |
dc.subject.lemac | Processament en paral·lel (Ordinadors) |
dc.subject.lemac | Càlcul intensiu (Informàtica) -- Estalvi d'energia |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1145/3472456.3472471 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://dl.acm.org/doi/10.1145/3472456.3472471 |
dc.rights.access | Open Access |
local.identifier.drac | 32106539 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/AGAUR/2017 SGR 1414 |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/H2020/955606/EU/DEEP – SOFTWARE FOR EXASCALE ARCHITECTURES/DEEP-SEA |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/H2020/730897/EU/Transnational Access Programme for a Pan-European Network of HPC Research Infrastructures and Laboratories for scientific computing/HPC-EUROPA3 |
local.citation.author | Navarro, A.; Lorenzon, A.; Ayguadé, E.; Beltran, V. |
local.citation.contributor | International Conference on Parallel Processing |
local.citation.pubplace | New York |
local.citation.publicationName | The 50th International Conference on Parallel Processing: August 9-12, 2021, hosted virtually from Chicago, Illinois, USA: main conference proceedings |
local.citation.startingPage | 1 |
local.citation.endingPage | 11 |