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Recent Submissions
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Artificial intelligence contribution to eHealth application
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference report
Restricted access - publisher's policyA presentation of the eHealth related concepts and challenges is done, together with an analysis on how the use of the Artificial Intelligence (AI) techniques can improve the management of the data generated by the eHealth ... -
Loopback strategy for TSN-compliant traffic queueing and shaping in automotive gateways
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Restricted access - publisher's policyIn this work, authors present a Hardware (HW)based loopback strategy which is a new paradigm in networkprocessing, for HW efficient and cost-effective integration of TimeSensitive Networking (TSN) functionalities within ... -
Traffic shaping engine for time sensitive networking integration within in-vehicle networks
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Restricted access - publisher's policyIn this work authors present a Traffic Shaping Engine (TSE) intended for the next generation of Time Sensitive Networking (TSN) compliant Network/System on Chip (NoC/SoC) devices, targeting especially the automotive industry. ... -
Elastic queueing engine for time sensitive networking
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Restricted access - publisher's policyIn this work we introduce the concept of Elastic Queueing Engine (EQE) for Time Sensitive Networking (TSN) which is a new networking-optimized queueing strategy designed to maximize Quality of Service (QoS) and usability ... -
Loopback strategy for in-vehicle network processing in automotive gateway network on chip
(Association for Computing Machinery (ACM), 2021)
Conference report
Restricted access - publisher's policyIn this work, authors introduce an innovative loopback strategy for In-Vehicle Network (IVN) processing in automotive gateway (GW) Network on Chip. The new proposed architecture is fully HW centric, and allows performing ... -
Hardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Restricted access - publisher's policyThis paper introduces a novel workflow for Distributed Spiking Neural Network Architecture (DSNA). As such, the hardware implementation of Single Instruction Multiple Data (SIMD)-based Spiking Neural Network (SNN) requires ... -
Complexity reduction of neural network model for local motion detection in motion stereo vision
(Springer, 2017)
Conference lecture
Restricted access - publisher's policySpatial perception, in which objects’ motion and positional relationship are recognized, is necessary for applications such as a walking robot and an autonomous car. One of the demanding features of spatial perception in ... -
Analog VLSI implementation of kernel-based classifiers
(Institute of Electrical and Electronics Engineers (IEEE), 1994)
Conference report
Open AccessKernel-based classifiers are neural networks (radial basis functions) where the probability densities of each class of data are first estimated, to be used thereafter to approximate Bayes boundaries between classes. Such ... -
Self-adaptive hardware architecture with parallel processing capabilities and dynamic reconfiguration
(Association for Computing Machinery (ACM), 2017)
Conference report
Restricted access - publisher's policyThis paper describes a new self-adaptive hardware architecture with fault tolerance capabilities and a development system that allows the creation of applications. This bioinspired architecture is based on an array of ... -
RTL Implementation And Analysis of Fixed Priority,Round Robin, and Matrix Arbiters for the NoC’sRouters
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Restricted access - publisher's policyNetworks-on-Chip (NoC) is an emerging on-chip interconnection centric platform that influences modern high speed communication infrastructure to improve the performance of many-core System-on-Chip (SoCs) designs. The core ... -
Approach to the modeling of LDO–assisted DC–DC voltage linear regulators
(Universidad de Málaga, 2017)
Conference report
Open AccessThis paper presents the design of a LDO-assisted DC-DC converters in Cadence Virtuoso based on a 350-nm CMOS technology. This kind of voltage regulators consists of a switching converter together with a classic or LDO (low ... -
On modeling of linear–assisted DC–DC voltage regulators
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference lecture
Open Access
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