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dc.contributor.authorSerrano Cases, Alejandro
dc.contributor.authorReina, Juan M.
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorMezzetti, Enrico
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.otherBarcelona Supercomputing Center
dc.identifier.citationSerrano Cases, A. [et al.]. Leveraging hardware QoS to control contention in the Xilinx Zynq UltraScale+ MPSoC. A: Euromicro Conference on Real-Time Systems. "33rd Euromicro Conference on Real-Time Systems (ECRTS 2021): July 5-9, 2021, Virtual Conference". Dagstuhl, Germany: Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2021, p. 3:1-3:26. ISBN 978-3-95977-192-4. DOI 10.4230/LIPIcs.ECRTS.2021.3.
dc.description.abstractThe interference co-running tasks generate on each other’s timing behavior continues to be one of the main challenges to be addressed before Multi-Processor System-on-Chip (MPSoCs) are fully embraced in critical systems like those deployed in avionics and automotive domains. Modern MPSoCs like the Xilinx Zynq UltraScale+ incorporate hardware Quality of Service (QoS) mechanisms that can help controlling contention among tasks. Given the distributed nature of modern MPSoCs, the route a request follows from its source (usually a compute element like a CPU) to its target (usually a memory) crosses several QoS points, each one potentially implementing a different QoS mechanism. Mastering QoS mechanisms individually, as well as their combined operation, is pivotal to obtain the expected benefits from the QoS support. In this work, we perform, to our knowledge, the first qualitative and quantitative analysis of the distributed QoS mechanisms in the Xilinx UltraScale+ MPSoC. We empirically derive QoS information not covered by the technical documentation, and show limitations and benefits of the available QoS support. To that end, we use a case study building on neural network kernels commonly used in autonomous systems in different real-time domains.
dc.description.sponsorshipThis work has been partially supported by the Spanish Ministry of Science and Innovation under grant PID2019-107255GB; the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 878752 (MASTECS) and the European Research Council (ERC) grant agreement No. 772773 (SuPerCom).
dc.format.extent26 p.
dc.publisherSchloss Dagstuhl - Leibniz-Zentrum für Informatik
dc.relation.ispartofseriesLeibniz International Proceedings in Informatics (LIPIcs)
dc.rightsAttribution 3.0 Spain
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshReal-time data processing
dc.subject.otherQuality of Service
dc.subject.otherReal-Time Systems
dc.subject.otherMulticore Contention
dc.titleLeveraging hardware QoS to control contention in the Xilinx Zynq UltraScale+ MPSoC
dc.typeConference report
dc.subject.lemacTemps real (Informàtica)
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/878752/EU/Multicore Analysis Service and Tools for Embedded Critical Systems/MASTECS
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/772773/EU/Sustainable Performance for High-Performance Embedded Computing Systems/SuPerCom
local.citation.contributorEuromicro Conference on Real-Time Systems
local.citation.pubplaceDagstuhl, Germany
local.citation.publicationName33rd Euromicro Conference on Real-Time Systems (ECRTS 2021): July 5-9, 2021, Virtual Conference

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Attribution 3.0 Spain
Except where otherwise noted, content on this work is licensed under a Creative Commons license : Attribution 3.0 Spain