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dc.contributor.authorMezzetti, Enrico
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.authorTabani, Hamid
dc.contributor.authorKosmidis, Leonidas
dc.contributor.otherBarcelona Supercomputing Center
dc.identifier.citationMezzetti, E. [et al.]. On the definition of resource sharing levels to understand and control the impact of contention in multicore processors. "SAE Technical Papers", Juny 2021, 2021-01-5055.
dc.description.abstractThe trend toward the adoption of a multiprocessor system on a chip (MPSoC) in critical real-time domains, like avionics or automotive, responds to the demand for increased computing performance to support advanced software functionalities. The other side of the coin is that MPSoCs challenge software timing analysis. This is so as co-running applications affect each other’s timing behavior on account of the interference incurred when accessing shared hardware resources, with the latter steadily increasing in number and complexity in every new generation of MPSoCs. For a solid and cost-contained software-timing validation approach, we contend that a taxonomy has to be developed to capture the different levels at which processors’ resources can be shared. Those levels are to be related to the conventional run-time software abstractions (e.g., task, thread, runnable) and the particular abstraction used to carry out contention analysis. From the standpoint of contention analysis, only the resources in those levels shared by the different run-time software entities need to be mastered and addressed by timing analysis, whereas the remaining resources can be safely disregarded. We tailor this approach to two of NVIDIA’s embedded platforms, TX2 and AGX Xavier, of particular relevance for the automotive domain. For the identified shared resources, we also characterize the contention that tasks can suffer and discuss the limitations and early approaches for modeling timing interference in shared hardware resources.
dc.description.sponsorshipThis work has been partially supported by the SpanishMinistry of Science and Innovation under grants PID2019-107255GB and FJCI-2017 -34095; and the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 878752 (MASTECS) and the European Research Council (ERC) grant agreement No. 772773 (SuPerCom).
dc.publisherSAE International
dc.rightsAttribution 3.0 Spain
dc.subjectÀrees temàtiques de la UPC::Informàtica::Hardware
dc.subject.lcshReal-time data processing
dc.subject.lcshEmbedded systems (Computer systems)
dc.subject.otherMulticore timing analysis
dc.subject.otherMulticore contention
dc.subject.otherSoftware timing
dc.subject.otherFreedom from interference
dc.subject.otherInterference channel
dc.titleOn the definition of resource sharing levels to understand and control the impact of contention in multicore processors
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/878752/EU/Multicore Analysis Service and Tools for Embedded Critical Systems/MASTECS
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/772773/EU/Sustainable Performance for High-Performance Embedded Computing Systems/SuPerCom
local.citation.publicationNameSAE Technical Papers

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Attribution 3.0 Spain
Except where otherwise noted, content on this work is licensed under a Creative Commons license : Attribution 3.0 Spain