VIA: A smart scratchpad for vector units with application to sparse matrix computations
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
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Sparse matrix operations are critical kernels in multiple application domains such as High Performance Computing, artificial intelligence and big data. Vector processing is widely used to improve performance on mathematical kernels with dense matrices. Unfortunately, existing vector architectures do not cope well with sparse matrix computations, achieving much lower performance in comparison with their dense counterparts.To overcome this limitation, we present the Vector Indexed Architecture (VIA), a novel hardware vector architecture that accelerates applications with irregular memory access patterns such as sparse matrix computations. There are two main bottlenecks when computing with sparse matrices: irregular memory accesses and index matching. VIA addresses these two bottlenecks with a smart scratchpad that is tightly coupled to the Vector Functional Units within the core.Thanks to this structure, VIA improves locality for sparse-dense computations and improves the index matching search process for sparse computations. As a result, VIA achieves significant performance speedup over highly optimized state-of-the-art C++ algebra libraries. On average, VIA outperforms sparse matrix vector multiplication, sparse matrix addition and sparse matrix matrix multiplication kernels by 4.22 ×, 6.14 × and 6.00 ×, respectively, when evaluated over a thousand sparse matrices that arise in real applications. In addition, we prove the generality of VIA by showing that it can accelerate histogram and stencil applications by 4.5 × and 3.5 ×, respectively.
CitationPavón, J. [et al.]. VIA: A smart scratchpad for vector units with application to sparse matrix computations. A: International Symposium on High-Performance Computer Architecture. "27th IEEE International Symposium on High Performance Computer Architecture: 27 February-3 March 2021, virtual event: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2021, p. 921-934. ISBN 978-0-7381-2337-0. DOI 10.1109/HPCA51647.2021.00081.
- Doctorat en Arquitectura de Computadors - Ponències/Comunicacions de congressos 
- HIPICS - High Performance Integrated Circuits and Systems - Ponències/Comunicacions de congressos 
- Computer Sciences - Ponències/Comunicacions de congressos 
- CAP - Grup de Computació d'Altes Prestacions - Ponències/Comunicacions de congressos 
- Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos [1.902]
- Departament d'Enginyeria Electrònica - Ponències/Comunicacions de congressos [1.679]