Sparse Matrix-Vector multiplication (SpMV) is an essential
kernel for parallel numerical applications. SpMV displays
sparse and irregular data accesses, which complicate its vectorization.
Such difficulties make SpMV to frequently experiment
non-optimal results when run on long vector ISAs exploiting
SIMD parallelism. In this context, the development of new optimizations
becomes fundamental to enable high performance
SpMV executions on emerging long vector architectures. In our
work, we improve the state-of-the-art SELL-C- sparse matrix
format by proposing several new optimizations for SpMV.
We target aggressive long vector architectures like the NEC
Vector Engine. By combining several optimizations, we obtain
an average 12% improvement over SELL-C- considering a
heterogeneous set of 24 matrices. Our optimizations boost
performance in long vector architectures since they expose a
high degree of SIMD parallelism.