Design for Testability methodologies applied to a RISC-Vprocessor
Tutor / directorMoll Echeto, Francisco de Borja
Document typeMaster thesis
Rights accessOpen Access
The decrease in the size of transistors and technology nodes has made manufacturing processes increasingly difficult and unreliable, Design for Test techniques provide measures to thoroughly test the manufactured device for quality and coverage. The main objective of this work is to apply those techniques to a processor, specifically the PreDRAC design, which is a RISC-V based SoC developed in collaboration with the BSC, CIC-IPN, IMB-CNM (CSIC) and UPC. To achieve this, DFT implementation steps through different phases of the elaboration of the preDRAC are performed, with the objective of maintaining a low impact on the area, timing and power values concerning the original design. During synthesis step the DFT configuration is defined, scan structures are added to improve the testability and compression structures are inserted to control scan chains. Then, the test patterns needed to detect defects are generated and simulated, studying two different types of analysis (static and dynamic). Finally, a Place&Route has been performed to elaborate a final layout. The final results show that DFT can successfully be integrated with the preDRAC SoC, with some overhead in the area and not degrading the timing constraints. The reports of the test pattern generation detailed that with the implemented design, high test coverage values are achieved. From the simulations carried out, we extract that all these test vectors have been successfully verified.
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