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Automatic safe data reuse detection for the WCET analysis of systems with data caches
dc.contributor.author | Segarra Flor, Juan |
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | Gran Tejero, Rubén |
dc.contributor.author | Viñals Yúfera, Victor |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
dc.date.accessioned | 2021-05-06T12:50:37Z |
dc.date.available | 2021-05-06T12:50:37Z |
dc.date.issued | 2020-10-19 |
dc.identifier.citation | Segarra, J. [et al.]. Automatic safe data reuse detection for the WCET analysis of systems with data caches. "IEEE access", 19 Octubre 2020, vol. 8, p. 192379-192392. |
dc.identifier.issn | 2169-3536 |
dc.identifier.uri | http://hdl.handle.net/2117/345260 |
dc.description.abstract | Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs, temporarily storing certain memory contents near the processor, in order that further accesses to such contents do not require costly memory transfers. Current worst-case data cache analysis methods focus on specific cache organizations (LRU, locked, ACDC, etc.). In this article, we analyze data reuse (in the worst case) as a property of the program, and thus independent of the data cache. Our analysis method uses Abstract Interpretation on the compiled program to extract, for each static load/store instruction, a linear expression for the address pattern of its data accesses, according to the Loop Nest Data Reuse Theory. Each data access expression is compared to that of prior (dominant) memory instructions to verify whether it presents a guaranteed reuse. Our proposal manages references to scalars, arrays, and non-linear accesses, provides both temporal and spatial reuse information, and does not require the exploration of explicit data access sequences. As a proof of concept we analyze the TACLeBench benchmark suite, showing that most loads/stores present data reuse, and how compiler optimizations affect it. Using a simple hit/miss estimation on our reuse results, the time devoted to data accesses in the worst case is reduced to 27% compared to an always-miss system, equivalent to a data hit ratio of 81%. With compiler optimization, such time is reduced to 6.5%. |
dc.description.sponsorship | This work was supported in part by MINECO/AEI/ERDF (EU) under Grant TIN2016-76635-C2-1-R, Grant TIN2017-86727-C2-1-R, and Grant PID2019-105660RB-C21; in part by the Aragón Government under Grant T58_20R research group; in part by the Generalitat de Catalunya under Grant 2017 SGR 786 and Grant FI-DGR 2015; and in part by the Construyendo Europa desde Aragón under Grant ERDF 2014-2020. |
dc.format.extent | 14 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.rights | Attribution 4.0 International |
dc.rights.uri | https://creativecommons.org/licenses/by/4.0/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Compilers (Computer programs) |
dc.subject.lcsh | Real-time data processing |
dc.subject.lcsh | Cache memory |
dc.subject.other | Real-time |
dc.subject.other | WCET |
dc.subject.other | Data-cache |
dc.subject.other | Data-reuse |
dc.title | Automatic safe data reuse detection for the WCET analysis of systems with data caches |
dc.type | Article |
dc.subject.lemac | Compiladors (Programes d'ordinador) |
dc.subject.lemac | Temps real (Informàtica) |
dc.subject.lemac | Memòria cau |
dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.identifier.doi | 10.1109/ACCESS.2020.3032145 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/9229458/ |
dc.rights.access | Open Access |
local.identifier.drac | 31265940 |
dc.description.version | Postprint (published version) |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO/TIN2016-76635-C2-1-R |
dc.relation.projectid | info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016/TIN2017-86727-C2-1-R/ES/MODELOS Y METODOS BASADOS EN GRAFOS PARA LA COMPUTACION EN GRAN ESCALA/ |
dc.relation.projectid | info:eu-repo/grantAgreement/AGAUR/2017 SGR 786 |
local.citation.author | Segarra, J.; Cortadella, J.; Gran, R.; Viñals, V. |
local.citation.publicationName | IEEE access |
local.citation.volume | 8 |
local.citation.startingPage | 192379 |
local.citation.endingPage | 192392 |
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