Design and implementation of a traffic injector for a bus-based space multicore

Abstract

Real-time multiprocessor systems have particular needs related to their design, verification, and validation. In particular, they have stringent requirements to prove that they will correctly perform their functionalities, on-time and minimizing system failures. Leading industrial applications such as aerospace vehicles or low orbit satellites require an increase of computing power while pursuing fast certification and a short time to market. These performance demands push for the adoption of multicore processors, generally with limited core counts, and connected with low-complexity interconnects, such as buses, to keep design complexity low and have some degree of isolation by construction among cores connected to different buses. The need for appropriate multicore interference timing verification and validation grows as those multicores are adopted for safety-relevant systems since evidence on the deadlines being met is needed. In particular, verification means are needed to assess whether deadlines can be met, and validation means are required in order to test that execution time bounds are not exceeded even under stress conditions. The lack of control and observability channels when using software-only interference generation tools leads to the overwhelming design and validation costs and inefficiencies since testing effort needs to increase to achieve some high coverage of realistic stressing conditions. However, still, there is not an easy way to assess whether such coverage is effectively achieved. All these barriers lead to less powerful and more expensive systems, as well as lower confidence in the guarantees achieved, and gives us a motivation to design a fully integrated hardware module that focuses on the generation of critical corner-cases traffic scenarios and eases the verification and validation of system interference bounds. This thesis's work focuses on implementing and integrating a hardware traffic injector that aims to go one step further into the stress-testing state of the art multiprocessor bus-based SoCs in real-time safety-critical applications. Our hardware module offers fine-grained controllability on a range of traffic patterns. It features a transparent software layer capable of interruption-based control and monitoring while maintaining a small memory footprint. AMBA AHB interfaces are provided for a wide market range of hardware platforms. The unit has been integrated with industry-proven SoCs such as NOEL-V (Cobham Gaisler) on novel space-graded hardware platforms as De-RISC and SELENE.