dc.contributor.author | Jamet, Alexandre Valentin |
dc.contributor.author | Álvarez Martí, Lluc |
dc.contributor.author | Jiménez, Daniel A. |
dc.contributor.author | Casas, Marc |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Barcelona Supercomputing Center |
dc.date.accessioned | 2021-04-13T10:24:39Z |
dc.date.available | 2021-04-13T10:24:39Z |
dc.date.issued | 2020 |
dc.identifier.citation | Jamet, A. V. [et al.]. Characterizing the impact of last-level cache replacement policies on big-data workloads. A: IEEE International Symposium on Workload Characterization. "2020 IEEE International Symposium on Workload Characterization: 27–29 October 2020, online event: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2020, p. 134-144. ISBN 978-1-7281-7645-1. DOI 10.1109/IISWC50251.2020.00022. |
dc.identifier.isbn | 978-1-7281-7645-1 |
dc.identifier.uri | http://hdl.handle.net/2117/343622 |
dc.description.abstract | The vast disparity between Last Level Cache (LLC) and memory latencies has motivated the need for efficient cache management policies. The computer architecture literature abounds with work on LLC replacement policy. Although these works greatly improve over the least-recently-used (LRU) policy, they tend to focus only on the SPEC CPU 2006 benchmark suite - and more recently on the SPEC CPU 2017 benchmark suite - for evaluation. However, these workloads are representative for only a subset of current High-Performance Computing (HPC) workloads. In this paper we evaluate the behavior of a mix of graph processing, scientific and industrial workloads (GAP, XSBench and Qualcomm) along with the well-known SPEC CPU 2006 and SPEC CPU 2017 workloads on state-of-the-art LLC replacement policies such as Multiperspective Reuse Prediction (MPPPB), Glider, Hawkeye, SHiP, DRRIP and SRRIP. Our evaluation reveals that, even though current state-of-the-art LLC replacement policies provide a significant performance improvement over LRU for both SPEC CPU 2006 and SPEC CPU 2017 workloads, those policies are hardly able to capture the access patterns and yield sensible improvement on current HPC and big data workloads due to their highly complex behavior. In addition, this paper introduces two new LLC replacement policies derived from MPPPB. The first proposed replacement policy, Multi-Sampler Multiperspective (MS-MPPPB), uses multiple samplers instead of a single one and dynamically selects the best-behaving sampler to drive reuse distance predictions. The second replacement policy presented in this paper, Multiperspective with Dynamic Features Selector (DS-MPPPB), selects the best behaving features among a set of 64 features to improve the accuracy of the predictions. On a large set of workloads that stress the LLC, MS-MPPPB achieves a geometric mean speed-up of 8.3% over LRU, while DS-MPPPB outperforms LRU by a geometric mean speedup of 8.0%. For big data and HPC workloads, the two proposed techniques present higher performance benefits than state-of-the-art approaches such as MPPPB, Glider and Hawkeye, which yield geometric mean speedups of 7.0%, 5.0% and 4.8% over LRU, respectively. |
dc.description.sponsorship | This work has been partially supported by the European Union’s Horizon 2020 research and innovation program under the Mont-Blanc 2020 project (grant agreement 779877). Lluc Alvarez has been partially supported by the Spanish Ministry of Economy, Industry and Competitiveness under the Juan de la Cierva Formacion fellowship number FJCI-2016-30984. Marc Casas has been partially supported by the Spanish Ministry of Economy, Industry and Competitiveness under Ramon y Cajal fellowship number RYC-2017-23269. This research was supported by National Science Foundation grant CCF-1912617, Semiconductor Research Corporation project 2936.001, and generous gifts from Intel Labs. |
dc.format.extent | 11 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Big data |
dc.subject.lcsh | Cache memory |
dc.subject.other | Cache management |
dc.subject.other | Graph processing |
dc.subject.other | Workload evaluation |
dc.subject.other | Micro-architecture |
dc.title | Characterizing the impact of last-level cache replacement policies on big-data workloads |
dc.type | Conference report |
dc.subject.lemac | Dades massives |
dc.subject.lemac | Memòria cau |
dc.identifier.doi | 10.1109/IISWC50251.2020.00022 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/9251256 |
dc.rights.access | Open Access |
local.identifier.drac | 30052019 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/H2020/779877/EU/Mont-Blanc 2020, European scalable, modular and power efficient HPC processor/Mont-Blanc 2020 |
local.citation.author | Jamet, A. V.; Álvarez, L.; Jiménez, D. A.; Casas, M. |
local.citation.contributor | IEEE International Symposium on Workload Characterization |
local.citation.publicationName | 2020 IEEE International Symposium on Workload Characterization: 27–29 October 2020, online event: proceedings |
local.citation.startingPage | 134 |
local.citation.endingPage | 144 |