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Technological layer
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2021-03-05T09:31:58Z |
dc.date.issued | 2020-10 |
dc.identifier.citation | Rubio, A.; Canal, R. Technological layer. A: "Cross-layer reliability of computing systems". Londres: The Institution of Engineering and Technology, 2020, p. 3-22. |
dc.identifier.isbn | 9781785617980 |
dc.identifier.uri | http://hdl.handle.net/2117/341025 |
dc.description.abstract | This chapter describes the fundamental characteristics of Complementary Metal-Oxide-Semiconductor (CMOS) technology, and how it can be assessed for system reliability studies. After some definitions, the dominating manufacturing technologies are described together with its advantages and disadvantages. Then, the core memory circuits present in today's computing systems are presented. Finally, the chapter provides an evaluation of these memory circuits when considering reliability across technology nodes. |
dc.format.extent | 20 p. |
dc.language.iso | eng |
dc.publisher | The Institution of Engineering and Technology |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject.lcsh | Computers--Circuits |
dc.subject.lcsh | Combinatorial optimization |
dc.subject.other | CMOS |
dc.subject.other | reliability |
dc.subject.other | manufacturing |
dc.subject.other | memory |
dc.subject.other | SRAM |
dc.subject.other | DRAM |
dc.subject.other | evaluation |
dc.subject.other | technology nodes |
dc.title | Technological layer |
dc.type | Part of book or chapter of book |
dc.subject.lemac | Ordinadors--Circuits |
dc.subject.lemac | Optimització combinatòria |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.group | Universitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems |
dc.identifier.doi | 10.1049/PBCS057E_ch1 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://www.theiet.org/ |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 29957437 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Rubio, A.; Canal, R. |
local.citation.pubplace | Londres |
local.citation.publicationName | Cross-layer reliability of computing systems |
local.citation.startingPage | 3 |
local.citation.endingPage | 22 |
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