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dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2021-03-05T09:31:58Z
dc.date.issued2020-10
dc.identifier.citationRubio, A.; Canal, R. Technological layer. A: "Cross-layer reliability of computing systems". Londres: The Institution of Engineering and Technology, 2020, p. 3-22.
dc.identifier.isbn9781785617980
dc.identifier.urihttp://hdl.handle.net/2117/341025
dc.description.abstractThis chapter describes the fundamental characteristics of Complementary Metal-Oxide-Semiconductor (CMOS) technology, and how it can be assessed for system reliability studies. After some definitions, the dominating manufacturing technologies are described together with its advantages and disadvantages. Then, the core memory circuits present in today's computing systems are presented. Finally, the chapter provides an evaluation of these memory circuits when considering reliability across technology nodes.
dc.format.extent20 p.
dc.language.isoeng
dc.publisherThe Institution of Engineering and Technology
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshComputers--Circuits
dc.subject.lcshCombinatorial optimization
dc.subject.otherCMOS
dc.subject.otherreliability
dc.subject.othermanufacturing
dc.subject.othermemory
dc.subject.otherSRAM
dc.subject.otherDRAM
dc.subject.otherevaluation
dc.subject.othertechnology nodes
dc.titleTechnological layer
dc.typePart of book or chapter of book
dc.subject.lemacOrdinadors--Circuits
dc.subject.lemacOptimització combinatòria
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems
dc.identifier.doi10.1049/PBCS057E_ch1
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://www.theiet.org/
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac29957437
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorRubio, A.; Canal, R.
local.citation.pubplaceLondres
local.citation.publicationNameCross-layer reliability of computing systems
local.citation.startingPage3
local.citation.endingPage22


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