Design of an Output Interface for an In-Memory-Computing CNN Accelerator

Abstract

Analog in-memory computing accelerators are one of the most promising solutions to reduce data movement limitations in deep neural networks (DNNs). While analog in-memory computing accelerators have been studied in many research works due to its growth potential, output interface layers of DNNs have not been studied in depth yet. This thesis proposes a binarizing batch normalization (BBN) scheme for the analog in-memory computing CNN accelerator that employs charge-domain compute designed in [1]. Implemented in 22 nm FDSOI, the design achieves energy efficiency of 1124 TOPS/W and throughput of 12418 GOPS, when implementing the in-memory solution followed by batch normalization.