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Multi-level dataflow-driven macro placement guided by RTL structure and analytical methods
dc.contributor.author | Vidal Obiols, Alexandre |
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | Petit Silvestre, Jordi |
dc.contributor.author | Galcerán Oms, Marc |
dc.contributor.author | Martorell Cid, Ferran |
dc.contributor.other | Universitat Politècnica de Catalunya. Doctorat en Computació |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
dc.date.accessioned | 2021-02-18T07:47:19Z |
dc.date.available | 2021-02-18T07:47:19Z |
dc.date.issued | 2021-12 |
dc.identifier.citation | Vidal, A. [et al.]. Multi-level dataflow-driven macro placement guided by RTL structure and analytical methods. "IEEE transactions on computer-aided design of integrated circuits and systems", Desembre 2021, vol. 40, núm. 12, p. 2542-2555. |
dc.identifier.issn | 0278-0070 |
dc.identifier.uri | http://hdl.handle.net/2117/340008 |
dc.description.abstract | When RTL designers define the hierarchy of a system, they exploit their knowledge about the conceptual abstractions devised during the design and the functional interactions between the logical components. This valuable information is often lost during physical synthesis. This paper proposes HiDaP, a novel multi-level algorithm that uses RTL information and analytical methods for the macro placement problem of modern designs dominated by multi-cycle connection pipelines. By taking advantage of the hierarchy tree, the netlist is divided into blocks containing macros and standard cells, and their dataflow affinity is inferred considering the register latency and flow width of their interaction. The layout is represented using slicing structures and generated with a top-down algorithm capable of handling blocks with both hard and soft components. An adaptive multi-objective cost function is used to simultaneously minimize wirelength, timing, overlap and distance to preferred locations, which can be user-defined or generated by analytic methods (spectral and force-directed). These techniques have been applied to a set of large industrial circuits and compared against state-of-theart commercial and academic placers, and also to handcrafted floorplans generated by expert back-end engineers. The proposed approach outperforms previous algorithmic methods and can produce solutions with better wirelength and timing than the best handcrafted floorplans. Post-routing layouts are almost brought to timing closure and DRC cleanness with minimal engineer modification, showing that the generated floorplans provide an excellent starting point for the physical design flow and contribute to reduce turn-around time significantly. |
dc.description.sponsorship | This work has been partially supported by a grant from Inphi Corporation and funds from the Spanish Ministry for Economy and Competitiveness and the European Union (FEDER funds) under grant TIN2017-86727-C2-1-R, and the Generalitat de Catalunya (2017 SGR 786). |
dc.format.extent | 14 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Integrated circuits -- Design and construction |
dc.subject.other | Timing |
dc.subject.other | Standards |
dc.subject.other | Integrated circuit modeling |
dc.subject.other | Layout |
dc.subject.other | Manuals |
dc.subject.other | Tools |
dc.subject.other | Shape |
dc.title | Multi-level dataflow-driven macro placement guided by RTL structure and analytical methods |
dc.type | Article |
dc.subject.lemac | Circuits integrats -- Disseny i construcció |
dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.identifier.doi | 10.1109/TCAD.2020.3047724 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/9309318 |
dc.rights.access | Open Access |
local.identifier.drac | 30574448 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016/TIN2017-86727-C2-1-R/ES/MODELOS Y METODOS BASADOS EN GRAFOS PARA LA COMPUTACION EN GRAN ESCALA/ |
dc.relation.projectid | info:eu-repo/grantAgreement/AGAUR/2017 SGR 786 |
local.citation.author | Vidal, A.; Cortadella, J.; Petit, J.; Galceran, M.; Martorell, F. |
local.citation.publicationName | IEEE transactions on computer-aided design of integrated circuits and systems |
local.citation.volume | 40 |
local.citation.number | 12 |
local.citation.startingPage | 2542 |
local.citation.endingPage | 2555 |
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