2D error correction for F/F based arrays using in-situ Real-Time Error Detection (RTD)
Document typeConference lecture
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
This work proposes in-situ Real-Time Error Detection (RTD): embedding hardware in a memory array for detecting a fault in the array when it occurs, rather than when it is read. RTD breaks the serialization between data access and error detection and, thus, it can speed-up the access-time of arrays that use in-line error-detection and correction. The approach can also reduce the time needed to root-cause array related bugs during post-silicon validation and product testing. The paper presents how to build RTD into an array with flip-flops to track in real-time the column-parity and introduces a two-dimensional RTD based error-correction scheme. As compared to SECDED, the evaluated scheme has comparable error-detection and correction strength and, depending on the array dimensions, the access time is reduced by 8-24% at an area and power overhead between 12-53% and 21-42% respectively.
CitationSazeides, Y. [et al.]. 2D error correction for F/F based arrays using in-situ Real-Time Error Detection (RTD). A: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. "DFT, 33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems: ESA-ESRIN, Italy (on-line virtual event), October 19–21, 2020". Institute of Electrical and Electronics Engineers (IEEE), 2020, p. 1-4. ISBN 978-1-7281-9457-8. DOI 10.1109/DFT50435.2020.9250878.
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