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dc.contributor.authorDabaghi Zarandi, Arezoo
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.authorReza Reshadinezhad, Mohammad
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2021-02-04T10:18:33Z
dc.date.issued2020
dc.identifier.citationDabaghi Zarandi, A.; Rubio, A.; Reza Reshadinezhad, M. A memristor-based quaternary memory with adaptive noise tolerance. A: Conference on Design of Circuits and Integrated Systems. "2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS): Segovia, Spain: november 18-20, 2020: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2020, ISBN 978-1-7281-9132-4. DOI 10.1109/DCIS51330.2020.9268675.
dc.identifier.isbn978-1-7281-9132-4
dc.identifier.urihttp://hdl.handle.net/2117/336877
dc.description.abstractConsidering the constraints of CMOS technology progress at the nano-domain, memristor technology is one of the preferred alternatives to merge with and substitute CMOS-based memory circuits. At the same time to increase the bandwidth of memories, increase storage density and decrease the interconnection complexity of circuits, multiple-valued logic (MVL) based circuit memories are being introduced as an efficient alternative. As resistive random access memory (ReRAM) is a non-volatile memory and memristor cells allow analog multilevel behavior, they are suitable device to store multiple-level bits of information. Different sources of noise and perturbances may affect the original values of data during the transferring and storing processes. A hybrid scenario based on CMOS and memristor technology is proposed here to recover the stored multiple noisy-perturbed values of resistive random-access memory in an efficient way. To show the correctness of the proposed method, affected images are simulated with Matlab software at system level showing its efficiency.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria elèctrica
dc.subject.lcshElectric circuits
dc.subject.otherMemristor
dc.subject.otherMVL
dc.subject.otherQuaternary
dc.subject.otherAdaptive Memory
dc.subject.otherApproximate
dc.titleA memristor-based quaternary memory with adaptive noise tolerance
dc.typeConference report
dc.subject.lemacCircuits elèctrics
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/DCIS51330.2020.9268675
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/9268675
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac30091186
dc.description.versionPostprint (author's final draft)
dc.date.lift10000-01-01
local.citation.authorDabaghi Zarandi, A.; Rubio, A.; Reza Reshadinezhad, M.
local.citation.contributorConference on Design of Circuits and Integrated Systems
local.citation.publicationName2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS): Segovia, Spain: november 18-20, 2020: proceedings


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