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dc.contributor.authorHaghi, Abbas
dc.contributor.authorÁlvarez Martí, Lluc
dc.contributor.authorPolo Bardés, Jorda
dc.contributor.authorDiamantopoulos, Dionysios
dc.contributor.authorHagleitner, Christoph
dc.contributor.authorMoretó Planas, Miquel
dc.contributor.otherUniversitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2021-02-01T12:12:30Z
dc.date.available2021-02-01T12:12:30Z
dc.date.issued2020
dc.identifier.citationHaghi, A. [et al.]. A hardware/software co-design of K-mer counting using a CAPI-enabled FPGA. A: International Conference on Field-Programmable Logic and Applications. "30th International Conference on Field-Programmable Logic and Applications, FPL 2020: 31 August - 4 September 2020, Gothenburg, Sweden: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2020, p. 57-64. ISBN 978-1-7281-9902-3. DOI 10.1109/FPL50879.2020.00020.
dc.identifier.isbn978-1-7281-9902-3
dc.identifier.urihttp://hdl.handle.net/2117/336276
dc.description.abstractAdvances in Next Generation Sequencing (NGS) technologies have caused the proliferation of genomic applications to detect DNA mutations and guide personalized medicine. These applications have an enormous computational cost due to the large amount of genomic data they process. Although leveraging FPGAs can improve the processing time of such amount of data, the limited memory capacity of FPGAs often restricts the potential gains. To overcome this limitation, IBM CAPI (Coherent Accelerator Processor Interface) supported platforms provide FPGAs with direct access to the CPU memory. This paper proposes a hardware/software co-design for k-mer counting, one of the most time-consuming phases of genomic applications. The proposed co-design targets CAPI-enabled FPGAs and is integrated into SMUFIN, a state-of-the-art reference-free method for finding DNA mutations. Results show that the proposed co-design outperforms the CPU-only design by a factor of 2.14×, it consumes 2.93× less energy, and it requires 1.57× less memory.
dc.description.sponsorshipThis work has been supported by the European HiPEAC Network of Excellence, by the Spanish Ministry of Science and Innovation (contract TIN2015-65316-P), by the Generalitat de Catalunya (contracts 2017-SGR-1414 and 2017-SGR1328), and by the IBM/BSC Deep Learning Center initiative. Ll. Alvarez has been supported by the Spanish Ministry of Economy, Industry and Competitiveness under the Juan de la Cierva Formacion fellowship No. FJCI-2016-30984. M. Moreto has been supported by the Spanish Ministry of Economy, Industry and Competitiveness under Ramon y Cajal fellowship No. RYC-2016-21104.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Aplicacions de la informàtica::Bioinformàtica
dc.subject.lcshGenomics
dc.subject.lcshField programmable gate arrays
dc.subject.lcshMemory management (Computer science)
dc.subject.otherFPGA
dc.subject.otherCo-design
dc.subject.otherAcceleration
dc.subject.otherCAPI
dc.subject.otherKmer
dc.subject.otherK-mer counting
dc.titleA hardware/software co-design of K-mer counting using a CAPI-enabled FPGA
dc.typeConference report
dc.subject.lemacGenòmica
dc.subject.lemacMatrius de portes programables per l'usuari
dc.subject.lemacGestió de memòria (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/FPL50879.2020.00020
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/9221608
dc.rights.accessOpen Access
local.identifier.drac30044482
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/
dc.relation.projectidinfo:eu-repo/grantAgreement/AGAUR/2017 SGR 1414
dc.relation.projectidinfo:eu-repo/grantAgreement/AGAUR/2017-SGR-1328
local.citation.authorHaghi, A.; Álvarez, L.; Polo, J.; Diamantopoulos, D.; Hagleitner, C.; Moreto, M.
local.citation.contributorInternational Conference on Field-Programmable Logic and Applications
local.citation.publicationName30th International Conference on Field-Programmable Logic and Applications, FPL 2020: 31 August - 4 September 2020, Gothenburg, Sweden: proceedings
local.citation.startingPage57
local.citation.endingPage64


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