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dc.contributor.authorAgosta, Giovanni
dc.contributor.authorFornaciari, William
dc.contributor.authorAtienza, David
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorCilardo, Alessandro
dc.contributor.authorFlich Cardo, José
dc.contributor.authorHernández Luz, Carles
dc.contributor.authorKulczewski, Michal
dc.contributor.authorMassari, Giuseppe
dc.contributor.authorTornero Gavilá, Rafael
dc.contributor.authorZapater Sancho, Marina
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2020-11-04T14:01:07Z
dc.date.available2022-06-26T00:32:22Z
dc.date.issued2020-09
dc.identifier.citationAgosta, G. [et al.]. The RECIPE approach to challenges in deeply heterogeneous high performance systems. "Microprocessors and microsystems", Setembre 2020, vol. 77, article 103185, p. 1-13.
dc.identifier.issn0141-9331
dc.identifier.otherhttp://arxiv.org/abs/2103.03044
dc.identifier.urihttp://hdl.handle.net/2117/331377
dc.description.abstractRECIPE (REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systems) is a recently started project funded within the H2020 FETHPC programme, which is expressly targeted at exploring new High-Performance Computing (HPC) technologies. RECIPE aims at introducing a hierarchical runtime resource management infrastructure to optimize energy efficiency and minimize the occurrence of thermal hotspots, while enforcing the time constraints imposed by the applications and ensuring reliability for both time-critical and throughput-oriented computation that run on deeply heterogeneous accelerator-based systems. This paper presents a detailed overview of RECIPE, identifying the fundamental challenges as well as the key innovations addressed by the project. In particular, the need for predictive reliability approaches to maximizing hardware lifetime and guarantee application performance is identified as the key concern for RECIPE. We address it through hierarchical resource management of the heterogeneous architectural components of the system, driven by estimates of the application latency and hardware reliability obtained respectively through timing analysis and modeling thermal properties and mean-time-to-failure of subsystems. We show the impact of prediction accuracy on the overheads imposed by the checkpointing policy, as well as a possible application to a weather forecasting use case.
dc.description.sponsorshipThe activities described in this article received funding from the European Union’s Horizon 2020 research and innovation programme under the FETHPC grant agreement no. 801137 RECIPE: REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systems.
dc.format.extent13 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 International
dc.rights©2020 Elsevier
dc.rights.urihttps://creativecommons.org/licenses/by-nc-nd/4.0/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshHardware -- Reliability
dc.subject.lcshHigh performance computing -- Energy consumption
dc.subject.otherHPC
dc.subject.otherHeterogeneous computing
dc.subject.otherRun-time management
dc.titleThe RECIPE approach to challenges in deeply heterogeneous high performance systems
dc.typeArticle
dc.subject.lemacOrdinadors -- Fiabilitat
dc.subject.lemacSuperordinadors -- Consum d'energia
dc.contributor.groupUniversitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems
dc.identifier.doi10.1016/j.micpro.2020.103185
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://www.sciencedirect.com/science/article/abs/pii/S0141933120303525
dc.rights.accessOpen Access
local.identifier.drac29329942
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/801137/EU/REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systems/RECIPE
local.citation.authorAgosta, G.; Fornaciari, W.; Atienza, D.; Canal, R.; Cilardo, A.; Flich, J.; Hernández, C.; Kulczewski, M.; Massari, G.; Tornero, R.; Zapater, M.
local.citation.publicationNameMicroprocessors and microsystems
local.citation.volume77
local.citation.numberarticle 103185
local.citation.startingPage1
local.citation.endingPage13


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