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dc.contributor.authorde Haro Ruiz, Juan Miguel
dc.contributor.authorBosch Pons, Jaume
dc.contributor.authorJiménez González, Daniel
dc.date.accessioned2020-10-30T12:40:08Z
dc.date.available2020-10-30T12:40:08Z
dc.date.issued2020-05
dc.identifier.citationDe Haro Ruiz, J.M.; Bosch Pons, J.; Jiménez González, D. Design and implementation of an architecture-aware hardware runtime for heterogeneous systems. A: . Barcelona Supercomputing Center, 2020, p. 57-58.
dc.identifier.urihttp://hdl.handle.net/2117/331025
dc.description.abstractParallel computing has become the norm to gain performance in multicore and heterogeneous systems. Many programming models allow to exploit this parallelism with easy to use tools. In this work we focus on task-based programming models. The parallelism is expressed with pieces of work called tasks that have data dependencies among them, and therefore have to be executed in a certain order. However, tasks that don’t depend on any other running task can be executed in parallel.
dc.format.extent2 p.
dc.languageen
dc.language.isoeng
dc.publisherBarcelona Supercomputing Center
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshHigh performance computing
dc.subject.otherheterogeneous systems
dc.subject.othertask-dependence analysis
dc.subject.otherHigh-performance computing
dc.subject.otherFPGA
dc.subject.othertask-based programming models
dc.titleDesign and implementation of an architecture-aware hardware runtime for heterogeneous systems
dc.typeConference report
dc.subject.lemacCàlcul intensiu (Informàtica)
dc.rights.accessOpen Access
local.citation.startingPage57
local.citation.endingPage58


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