Lightweight protection of cryptographic hardware accelerators against differential fault analysis
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
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Hardware acceleration circuits for cryptographic algorithms are largely deployed in a wide range of products. The HW implementations of such algorithms often suffer from a number of vulnerabilities that expose systems to several attacks, e.g., differential fault analysis (DFA). The challenge for designers is to protect cryptographic accelerators in a cost-effective and power-efficient way. In this paper, we propose a lightweight technique for protecting hardware accelerators implementing AES and SHA-2 (which are two widely used NIST standards) against DFA. The proposed technique exploits partial redundancy to first detect the occurrence of a fault and then to react to the attack by obfuscating the output values. An experimental campaign demonstrated that the overhead introduced is 8.32% for AES and 3.88% for SHA-2 in terms of area, 0.81% for AES and 12.31% for SHA-2 in terms of power with no working frequency reduction. Moreover, a comparative analysis showed that our proposal outperforms the most recent related countermeasures.
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CitationLasheras, A. [et al.]. Lightweight protection of cryptographic hardware accelerators against differential fault analysis. A: IEEE International Symposium on On-Line Testing and Robust System Design. "2020 26th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS): July 13-16, 2020, virtual edition: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2020, p. 1-6. ISBN 978-1-7281-8187-5. DOI 10.1109/IOLTS50870.2020.9159720.