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dc.contributor.authorSalami, Behzad
dc.contributor.authorOnural, Erhan Baturay
dc.contributor.authorYuksel, Ismail Emir
dc.contributor.authorKoc, Fahrettin
dc.contributor.authorErgin, Oguz
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorSarbazi-Azad, Hamid
dc.contributor.authorMutlu, Onur
dc.contributor.otherUniversitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2020-10-21T11:39:54Z
dc.date.available2020-10-21T11:39:54Z
dc.date.issued2020
dc.identifier.citationSalami, B. [et al.]. An experimental study of reduced-voltage operation in modern FPGAs for neural network acceleration. A: Annual IEEE/IFIP International Conference on Dependable Systems and Networks. "50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks: 29 June-2 July 2020, Valencia, Spain: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2020, p. 138-149. ISBN 978-1-7281-5809-9. DOI 10.1109/DSN48063.2020.00032.
dc.identifier.isbn978-1-7281-5809-9
dc.identifier.otherhttps://arxiv.org/abs/2005.03451
dc.identifier.urihttp://hdl.handle.net/2117/330567
dc.description.abstractWe empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing faults due to excessive circuit latency increase. We evaluate the reliability-power trade-off for such accelerators. Specifically, we experimentally study the reduced-voltage operation of multiple components of real FPGAs, characterize the corresponding reliability behavior of CNN accelerators, propose techniques to minimize the drawbacks of reduced-voltage operation, and combine undervolting with architectural CNN optimization techniques, i.e., quantization and pruning. We investigate the effect ofenvironmental temperature on the reliability-power trade-off of such accelerators. We perform experiments on three identical samples of modern Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification CNN benchmarks. This approach allows us to study the effects of our undervolting technique for both software and hardware variability. We achieve more than 3X power-efficiency (GOPs/W ) gain via undervolting. 2.6X of this gain is the result of eliminating the voltage guardband region, i.e., the safe voltage region below the nominal level that is set by FPGA vendor to ensure correct functionality in worst-case environmental and circuit conditions. 43% of the power-efficiency gain is due to further undervolting below the guardband, which comes at the cost of accuracy loss in the CNN accelerator. We evaluate an effective frequency underscaling technique that prevents this accuracy loss, and find that it reduces the power-efficiency gain from 43% to 25%.
dc.description.sponsorshipThe work done for this paper was partially supported by a HiPEAC Collaboration Grant funded by the H2020 HiPEAC Project under grant agreement No. 779656. The research leading to these results has received funding from the European Union’s Horizon 2020 Programme under the LEGaTO Project (www.legato-project.eu), grant agreement No. 780681.
dc.format.extent12 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors
dc.subject.lcshField programmable gate arrays
dc.subject.lcshNeural networks (Computer science)
dc.subject.otherReliability
dc.subject.otherCircuit faults
dc.subject.otherPower demand
dc.subject.otherQuantization (signal)
dc.subject.otherHardware
dc.subject.otherTraining
dc.titleAn experimental study of reduced-voltage operation in modern FPGAs for neural network acceleration
dc.typeConference report
dc.subject.lemacMatrius de portes programables per l'usuari
dc.subject.lemacXarxes neuronals (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/DSN48063.2020.00032
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/9153393
dc.rights.accessOpen Access
local.identifier.drac29342164
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/779656/EU/High Performance and Embedded Architecture and Compilation/HiPEAC
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/780681/EU/Low Energy Toolset for Heterogeneous Computing/LEGaTO
local.citation.authorSalami, B.; Onural, E.; Yuksel, I.; Koc, F.; Ergin, O.; Cristal, A.; Unsal, O.; Sarbazi-Azad, H.; Mutlu, O.
local.citation.contributorAnnual IEEE/IFIP International Conference on Dependable Systems and Networks
local.citation.publicationName50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks: 29 June-2 July 2020, Valencia, Spain: proceedings
local.citation.startingPage138
local.citation.endingPage149


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