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dc.contributor.authorBarredo Ferreira, Adrián
dc.contributor.authorBeard, Jonathan C.
dc.contributor.authorMoreto Planas, Miquel
dc.contributor.otherUniversitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2020-10-21T10:20:27Z
dc.date.available2020-10-21T10:20:27Z
dc.date.issued2019
dc.identifier.citationBarredo, A.; Beard, J.; Moreto, M. POSTER: SPiDRE: accelerating sparse memory access patterns. A: International Conference on Parallel Architectures and Compilation Techniques. "2019 28th International Conference on Parallel Architectures and Compilation Techniques, PACT 2019: Seattle, Washington, United States, 21-25 September 2019: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 482-483. ISBN 978-1-7281-3613-4. DOI 10.1109/PACT.2019.00056.
dc.identifier.isbn978-1-7281-3613-4
dc.identifier.urihttp://hdl.handle.net/2117/330537
dc.description.abstractDevelopment in process technology has led to an exponential increase in processor speed and memory capacity. However, memory latencies have not improved as dramatically and represent a well-known problem in computer architecture. Cache memories provide more bandwidth with lower latencies than main memories but they are capacity limited. Locality-friendly applications benefit from a large and deep cache hierarchy. Nevertheless, this is a limited solution for applications suffering from sparse and irregular memory access patterns, such as data analytics. In order to accelerate them, we should maximize usable bandwidth, reduce latency and maximize moved data reuse. In this work we explore the Sparse Data Rearrange Engine (SPiDRE), a novel hardware approach to accelerate these applications through near-memory data reorganization.
dc.description.sponsorshipThis work has been supported by the Spanish Ministry of Science and Innovation (contract TIN2015-65316-P, Ramon y Cajal fellowship number RYC-2016-21104 and FPI fellowship number BES-2017-080635), and by the Arm-BSC Centre of Excellence initiative.
dc.format.extent2 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMemory management (Computer science)
dc.subject.otherPrefetching
dc.subject.otherBandwidth
dc.subject.otherAcceleration
dc.subject.otherNeon
dc.subject.otherComputer architecture
dc.subject.otherCoherence
dc.subject.otherCache memory
dc.titlePOSTER: SPiDRE: accelerating sparse memory access patterns
dc.typeConference lecture
dc.subject.lemacGestió de memòria (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/PACT.2019.00056
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8891062
dc.rights.accessOpen Access
local.identifier.drac28141944
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/1PE/TIN2015-65316-P
dc.relation.projectidinfo:eu-repo/grantAgreement/AEI/RYC-2016-21104
local.citation.authorBarredo, A.; Beard, J.; Moreto, M.
local.citation.contributorInternational Conference on Parallel Architectures and Compilation Techniques
local.citation.publicationName2019 28th International Conference on Parallel Architectures and Compilation Techniques, PACT 2019: Seattle, Washington, United States, 21-25 September 2019: proceedings
local.citation.startingPage482
local.citation.endingPage483


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