POSTER: SPiDRE: accelerating sparse memory access patterns
Document typeConference lecture
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
Development in process technology has led to an exponential increase in processor speed and memory capacity. However, memory latencies have not improved as dramatically and represent a well-known problem in computer architecture. Cache memories provide more bandwidth with lower latencies than main memories but they are capacity limited. Locality-friendly applications benefit from a large and deep cache hierarchy. Nevertheless, this is a limited solution for applications suffering from sparse and irregular memory access patterns, such as data analytics. In order to accelerate them, we should maximize usable bandwidth, reduce latency and maximize moved data reuse. In this work we explore the Sparse Data Rearrange Engine (SPiDRE), a novel hardware approach to accelerate these applications through near-memory data reorganization.
CitationBarredo, A.; Beard, J.; Moreto, M. POSTER: SPiDRE: accelerating sparse memory access patterns. A: International Conference on Parallel Architectures and Compilation Techniques. "2019 28th International Conference on Parallel Architectures and Compilation Techniques, PACT 2019: Seattle, Washington, United States, 21-25 September 2019: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 482-483. ISBN 978-1-7281-3613-4. DOI 10.1109/PACT.2019.00056.
- Doctorat en Arquitectura de Computadors - Ponències/Comunicacions de congressos 
- Computer Sciences - Ponències/Comunicacions de congressos 
- CAP - Grup de Computació d'Altes Prestacions - Ponències/Comunicacions de congressos 
- Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos [1.596]
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