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A novel FPGA-based high throughput accelerator for binary search trees
dc.contributor.author | Melikoglu, Oyku |
dc.contributor.author | Ergin, Oguz |
dc.contributor.author | Salami, Behzad |
dc.contributor.author | Pavón Rivera, Julián |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.other | Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Barcelona Supercomputing Center |
dc.date.accessioned | 2020-10-20T07:54:01Z |
dc.date.available | 2020-10-20T07:54:01Z |
dc.date.issued | 2019 |
dc.identifier.citation | Melikoglu, O. [et al.]. A novel FPGA-based high throughput accelerator for binary search trees. A: International Conference on High Performance Computing and Simulation. "17th International Conference on High Performance Computing & Simulation, HPCS 2019: Dublin, Ireland, July 15-19, 2019". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 612-619. ISBN 978-1-7281-4484-9. DOI 10.1109/HPCS48598.2019.9188158. |
dc.identifier.isbn | 978-1-7281-4484-9 |
dc.identifier.uri | http://hdl.handle.net/2117/330458 |
dc.description.abstract | This paper presents a deeply pipelined and massively parallel Binary Search Tree (BST) accelerator for Field Programmable Gate Arrays (FPGAs). Our design relies on the extremely parallel on-chip memory, or Block RAMs (BRAMs) architecture of FPGAs. To achieve significant throughput for the search operation on BST, we present several novel mechanisms including tree duplication as well as horizontal, duplicated, and hybrid (horizontal-vertical) tree partitioning. Also, we present efficient techniques to decrease the stalling rates that can occur during the parallel tree search. By combining these techniques and implementations on Xilinx Virtex-7 VC709 platform, we achieve up to 8X throughput improvement gain in comparison to the baseline implementation, i.e., a fully-pipelined FPGA-based accelerator. |
dc.description.sponsorship | The research leading to these results has received funding from the European Union’s Horizon 2020 Program under the LEGaTO Project (www.legato-project.eu), grant agreement nº 780681. |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Field programmable gate arrays |
dc.subject.lcsh | Logic design |
dc.subject.other | FPGA |
dc.subject.other | Hardware accelerator |
dc.subject.other | Parallel search |
dc.subject.other | Binary search tree (BST) |
dc.title | A novel FPGA-based high throughput accelerator for binary search trees |
dc.type | Conference report |
dc.subject.lemac | Matrius de portes programables per l'usuari |
dc.subject.lemac | Estructura lògica |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/HPCS48598.2019.9188158 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/9188158 |
dc.rights.access | Open Access |
local.identifier.drac | 29519734 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/H2020/780681/EU/Low Energy Toolset for Heterogeneous Computing/LEGaTO |
local.citation.author | Melikoglu, O.; Ergin, O.; Salami, B.; Pavón, J.; Unsal, O.; Cristal, A. |
local.citation.contributor | International Conference on High Performance Computing and Simulation |
local.citation.publicationName | 17th International Conference on High Performance Computing & Simulation, HPCS 2019: Dublin, Ireland, July 15-19, 2019 |
local.citation.startingPage | 612 |
local.citation.endingPage | 619 |