A novel FPGA-based high throughput accelerator for binary search trees
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
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This paper presents a deeply pipelined and massively parallel Binary Search Tree (BST) accelerator for Field Programmable Gate Arrays (FPGAs). Our design relies on the extremely parallel on-chip memory, or Block RAMs (BRAMs) architecture of FPGAs. To achieve significant throughput for the search operation on BST, we present several novel mechanisms including tree duplication as well as horizontal, duplicated, and hybrid (horizontal-vertical) tree partitioning. Also, we present efficient techniques to decrease the stalling rates that can occur during the parallel tree search. By combining these techniques and implementations on Xilinx Virtex-7 VC709 platform, we achieve up to 8X throughput improvement gain in comparison to the baseline implementation, i.e., a fully-pipelined FPGA-based accelerator.
CitationMelikoglu, O. [et al.]. A novel FPGA-based high throughput accelerator for binary search trees. A: International Conference on High Performance Computing and Simulation. "17th International Conference on High Performance Computing & Simulation, HPCS 2019: Dublin, Ireland, July 15-19, 2019". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 612-619. ISBN 978-1-7281-4484-9. DOI 10.1109/HPCS48598.2019.9188158.
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- Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos [1.773]