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dc.contributor.authorPapadimitriou, George
dc.contributor.authorChatzidimitriou, Athanansios
dc.contributor.authorGizopoulos, Dimitris
dc.contributor.authorReddi, Vijay Janapa
dc.contributor.authorLeng, Jingwen
dc.contributor.authorSalami, Behzad
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.otherUniversitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2020-10-15T07:29:56Z
dc.date.available2020-10-15T07:29:56Z
dc.date.issued2020-06
dc.identifier.citationPapadimitriou, G. [et al.]. Exceeding conservative limits: A consolidated analysis on modern hardware margins. "IEEE transactions on device and materials reliability", Juny 2020, vol. 20, núm. 2, p. 341-350.
dc.identifier.issn1530-4388
dc.identifier.urihttp://hdl.handle.net/2117/330274
dc.description© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
dc.description.abstractModern large-scale computing systems (data centers, supercomputers, cloud and edge setups and high-end cyber-physical systems) employ heterogeneous architectures that consist of multicore CPUs, general-purpose many-core GPUs, and programmable FPGAs. The effective utilization of these architectures poses several challenges, among which a primary one is power consumption. Voltage reduction is one of the most efficient methods to reduce power consumption of a chip. With the galloping adoption of hardware accelerators (i.e., GPUs and FPGAs) in large datacenters and other large-scale computing infrastructures, a comprehensive evaluation of the safe voltage reduction levels for each different chip can be employed for efficient reduction of the total power. We present a survey of recent studies in voltage margins reduction at the system level for modern CPUs, GPUs and FPGAs. The pessimistic voltage guardbands inserted by the silicon vendors can be exploited in all devices for significant power savings. On average, voltage reduction can reach 12% in multicore CPUs, 20% in manycore GPUs and 39% in FPGAs.
dc.description.sponsorshipThe research leading to results in the CPU part was funded by the EU H2020 Programme under the UniServer project (http://www.uniserver2020.eu), grant agreement n◦ 688540. Also, the research leading to results in FPGA part was funded by the EU H2020 Programme under the LEGaTO project (https://legato-project.eu), grant agreement n◦ 780681.
dc.format.extent10 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshField programmable gate arrays
dc.subject.lcshMicroprocessors -- Energy consumption
dc.subject.lcshGraphics processing units
dc.subject.otherVoltage margins
dc.subject.otherPower consumption
dc.subject.otherEnergy efficiency
dc.subject.otherMulticore CPU
dc.subject.otherMany-core GPU
dc.subject.otherFPGA
dc.subject.otherAccelerators
dc.titleExceeding conservative limits: A consolidated analysis on modern hardware margins
dc.typeArticle
dc.subject.lemacMatrius de portes programables per l'usuari
dc.subject.lemacMicroprocessadors -- Consum d'energia
dc.subject.lemacUnitats de processament gràfic
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/TDMR.2020.2989813
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/abstract/document/9076808
dc.rights.accessOpen Access
local.identifier.drac28091256
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/780681/EU/Low Energy Toolset for Heterogeneous Computing/LEGaTO
local.citation.authorPapadimitriou, G.; Chatzidimitriou, A.; Gizopoulos, D.; Reddi, V.; Leng, J.; Salami, B.; Unsal, O.; Cristal, A.
local.citation.publicationNameIEEE transactions on device and materials reliability
local.citation.volume20
local.citation.number2
local.citation.startingPage341
local.citation.endingPage350


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