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dc.contributor.authorBosch Pons, Jaume
dc.contributor.authorFilgueras Izquierdo, Antonio
dc.contributor.authorVidal, Miquel
dc.contributor.authorJiménez González, Daniel
dc.contributor.authorÁlvarez Martínez, Carlos
dc.contributor.authorMartorell, Xavier
dc.contributor.otherUniversitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2020-10-02T13:14:55Z
dc.date.issued2017
dc.identifier.citationBosch, J. [et al.]. Exploiting parallelism on GPUs and FPGAs with OmpSs. A: Workshop on AutotuniNg and adaptivity AppRoaches for Energy efficient HPC Systems. "ANDARE'2017: 1st Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems: Portland, Oregon, USA: Sept. 9, 2017". New York: Association for Computing Machinery (ACM), 2017, p. 1-5. ISBN 978-1-4503-5363-2. DOI 10.1145/3152821.3152880.
dc.identifier.isbn978-1-4503-5363-2
dc.identifier.urihttp://hdl.handle.net/2117/329729
dc.description.abstractThis paper presents the OmpSs approach to deal with heterogeneous programming on GPU and FPGA accelerators. The OmpSs programming model is based on the Mercurium compiler and the Nanos++ runtime. Applications are annotated with compiler directives specifying task-based parallelism. The Mercurium compiler transforms the code to exploit the parallelism in the SMP host cores, and also to spawn work on CUDA/OpenCL devices, and FPGA accelerators. For the CUDA/OpenCL devices, the programmer needs only to insert the annotations and provide the kernel function to be compiled by the native CUDA/OpenCL compiler. In the case of the FPGAs, OmpSs uses the High-Level Synthesis tools from FPGA vendors to generate the IP configurations for the FPGA. In this paper we present the performance obtained on the matrix multiply benchmark in the Xilinx Zynq Ultrascale+, as a result of using OmpSs on this benchmark.
dc.description.sponsorshipThis work is partially supported by the European Union H2020 program through the AXIOM project (grant ICT-01-2014 GA 645496) and HiPEAC (GA 687698), by the Spanish Government through Programa Severo Ochoa (SEV-2011-0067), by the Spanish Ministerio de Economia y Competitividad under contract Computacion de Altas Prestaciones VII (TIN2015-65316-P), and the Departament d’Innovacio, Universitats i Empresa de la Generalitat de Catalunya, under project MPEXPAR: Models de Programacio i Entorns d’Execucio Paral·lels (2014-SGR-1051).
dc.format.extent5 p.
dc.language.isoeng
dc.publisherAssociation for Computing Machinery (ACM)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshParallel programming (Computer science)
dc.subject.otherOmpSs programming model
dc.subject.otherParallelism
dc.subject.otherGPU
dc.subject.otherFPGA
dc.titleExploiting parallelism on GPUs and FPGAs with OmpSs
dc.typeConference report
dc.subject.lemacProgramació en paral·lel (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1145/3152821.3152880
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://dl.acm.org/doi/10.1145/3152821.3152880
dc.rights.accessOpen Access
local.identifier.drac28996942
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/645496/EU/Agile, eXtensible, fast I%2FO Module for the cyber-physical era/AXIOM
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/687698/EU/High Performance and Embedded Architecture and Compilation/HiPEAC
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/
dc.relation.projectidinfo:eu-repo/grantAgreement/AGAUR/PRI2010-2013/2014 SGR 1051
dc.date.lift10000-01-01
local.citation.authorBosch, Jaume; Filgueras, A.; Vidal, Miquel; Jimenez, D.; Alvarez, C.; Martorell, X.
local.citation.contributorWorkshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems
local.citation.pubplaceNew York
local.citation.publicationNameANDARE'2017: 1st Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems: Portland, Oregon, USA: Sept. 9, 2017
local.citation.startingPage1
local.citation.endingPage5


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