Rethinking cycle accurate DRAM simulation
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Cita com:
hdl:2117/329626
Tipus de documentText en actes de congrés
Data publicació2019
EditorAssociation for Computing Machinery (ACM)
Condicions d'accésAccés obert
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Abstract
Cycle accurate DRAM simulations have been the dominating architecture simulation model for DRAM for a long time. Although accurate, its poor simulation speed has not improved for years while a lot of other architecture simulators such as CPU and cache simulators have moved away from cycle-accurate models for better performance. In this paper, we discuss limitations of cycle-accurate DRAM models, through simulation experiments, we show that cycle-accurate DRAM simulator is becoming a dominant part of overall simulation time when paired with modern CPU simulators. We also demonstrate the inherent inflexibility of cycle-accurate models becomes the roadblock for faster simulation speed and integration with other non-cycle-accurate simulation frameworks. Finally, we discuss alternative modeling techniques for DRAM simulation and point out potential pathways to further DRAM simulation technique.
CitacióLi, S. [et al.]. Rethinking cycle accurate DRAM simulation. A: International Symposium on Memory Systems. "MEMSYS 2019: proceedings of the International Symposium on Memory Systems: Washington DC, September 30–October 3, 2019". New York: Association for Computing Machinery (ACM), 2019, p. 184-191. ISBN 978-1-4503-7206-0. DOI 10.1145/3357526.3357539.
ISBN978-1-4503-7206-0
Versió de l'editorhttps://dl.acm.org/doi/abs/10.1145/3357526.3357539
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DRAM.pdf | 698,4Kb | Visualitza/Obre |