Breaking master-slave model between host and FPGAs
Document typeConference lecture
PublisherAssociation for Computing Machinery (ACM)
Rights accessOpen Access
European Commission's projectEPEEC - European joint Effort toward a Highly Productive Programming Environment for Heterogeneous Exascale Computing (EPEEC) (EC-H2020-801051)
This paper proposes to enhance current task-based programming models by breaking their current master-slave approach between the main processor and its hardware accelerators. As a proof-of-concept, it presents an extension of the OmpSs@FPGA toolchain that allows the tasks offloaded into the FPGA to create and synchronize nested tasks on their own without involving the host. Those FPGA spawned tasks may target the host to execute code not suitable for the FPGA, like system calls or I/O operations; or target other kernel accelerators inside the same FPGA. In addition to the programmability benefits of this new feature, the proposed system presents significant performance improvements and a better productivity over the classical master-slave approach.
CitationBosch, J. [et al.]. Breaking master-slave model between host and FPGAs. A: ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. "PPoPP'20: Proceedings of the 2020 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming: San Diego, CA, USA: 22-26 February 2020". New York: Association for Computing Machinery (ACM), 2020, p. 419-420. ISBN 978-1-4503-6818-6. DOI 10.1145/3332466.3374545.
- Doctorat en Arquitectura de Computadors - Ponències/Comunicacions de congressos 
- Computer Sciences - Ponències/Comunicacions de congressos 
- CAP - Grup de Computació d'Altes Prestacions - Ponències/Comunicacions de congressos 
- Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos [1.674]
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