Design and implementation of an architecture-aware hardware runtime for heterogeneous systems
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Cita com:
hdl:2117/329018
Tipus de documentProjecte Final de Màster Oficial
Data2020-06-30
Condicions d'accésAccés obert
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Abstract
In order to keep accelerating applications, it is a common trend to use heterogeneous systems with specialized hardware. They offer the best trade-off in performance and power consumption at the cost of programmability. Moreover, the number of cores in Symmetric Multiprocessors (SMP) architectures is increasing to keep up with the computation needs of emerging applications. As a result, handling such hardware accelerators and cores is becoming a challenge. Task-based programming models offer to the programmer an easy way to expose and exploit the parallelism of an application. A task is a unit of work which can be executed by a single thread on a processor core or an accelerator. The user can annotate tasks with input and output data requirements that can be used by the runtime to detect dependencies between tasks and establish a correct implicit task execution order. A software runtime is responsible to detect these dependencies to be able to ensure correctness and also exploit any existing parallelism based on the programmer's annotation in the application. The overhead introduced by this runtime becomes noticeable as the number of compute units increase or the task execution time becomes smaller. To keep up with the number of cores/accelerators and speedup fine-grained parallelism in an efficient way, in this work we propose, design and implement Picos Daviu, a hardware dependence manager for task-based programming models. Picos Daviu proposal is able to handle task dependencies and determine which can be executed in parallel. First design has been implemented in SystemVerilog, and integrated to OmpSs@FPGA programming model, which provides a scheduler and a communication protocol to deliver tasks to hardware accelerators implemented in FPGAs. Picos Daviu has result in a mechanism to deal with distributed systems with FPGAs connected to the cloud and embedded FPGAs in a multicore chip. The autonomy of Picos Davius helps you to manage these systems without the need of a close and attached host.
MatèriesHigh performance computing, Adaptive computing systems, Càlcul intensiu (Informàtica), Sistemes adaptatius (Informàtica)
TitulacióMÀSTER UNIVERSITARI EN INNOVACIÓ I RECERCA EN INFORMÀTICA (Pla 2012)
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