Show simple item record

dc.contributor.authorDabaghi Zarandi, Arezoo
dc.contributor.authorReza Reshadinezhad, Mohammad
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2020-09-18T09:18:42Z
dc.date.available2020-09-18T09:18:42Z
dc.date.issued2020-01-01
dc.identifier.citationDabaghi, A.; Reza, M.; Rubio, A. A systematic method to design efficient ternary high performance CNTFET-based logic cells. "IEEE access", 1 Gener 2020, vol. 8, p. 58585.
dc.identifier.issn2169-3536
dc.identifier.urihttp://hdl.handle.net/2117/328909
dc.description.abstractThe huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to consider multiple-valued logic (MVL) alternatives. Features of Carbon Nanotube Field-Effect Transistors (CNTFETs) make this technology a potential candidate to implement MVL circuits. In this article, a new systematic methodology is proposed to design ternary logic block circuits based on CNTFETs. The methodology is applied to the design of two basic logic circuits, a half adder and a 1-digit multiplier, which are evaluated through HSPICE simulations. Simulation results indicate improvements over current equivalents in transistor count and PDP mean with the half adder version of 19.2%, and 74.07% respectively, and with the 1-digit multiplier of 24.67% and 81.12% respectively.
dc.format.extent1 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Energies::Eficiència energètica
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshEnergy conservation
dc.subject.lcshIntegrated circuits
dc.subject.otherCNTFET
dc.subject.otherMVL
dc.subject.otherTernary
dc.subject.otherHalf adder
dc.subject.otherMultiplier
dc.titleA systematic method to design efficient ternary high performance CNTFET-based logic cells
dc.typeArticle
dc.subject.lemacEnergia -- Estalvi
dc.subject.lemacCircuits integrats
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/ACCESS.2020.2982738
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/9044858
dc.rights.accessOpen Access
local.identifier.drac28852397
dc.description.versionPostprint (published version)
local.citation.authorDabaghi, A.; Reza, M.; Rubio, A.
local.citation.publicationNameIEEE access
local.citation.volume8
local.citation.startingPage58585
local.citation.endingPage58585


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record