A systematic method to design efficient ternary high performance CNTFET-based logic cells
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to consider multiple-valued logic (MVL) alternatives. Features of Carbon Nanotube Field-Effect Transistors (CNTFETs) make this technology a potential candidate to implement MVL circuits. In this article, a new systematic methodology is proposed to design ternary logic block circuits based on CNTFETs. The methodology is applied to the design of two basic logic circuits, a half adder and a 1-digit multiplier, which are evaluated through HSPICE simulations. Simulation results indicate improvements over current equivalents in transistor count and PDP mean with the half adder version of 19.2%, and 74.07% respectively, and with the 1-digit multiplier of 24.67% and 81.12% respectively.
CitationDabaghi, A.; Reza, M.; Rubio, A. A systematic method to design efficient ternary high performance CNTFET-based logic cells. "IEEE access", 1 Gener 2020, vol. 8, p. 58585.