Reports de recerca: Enviaments recents

Ara es mostren els items 13-24 de 58

    • Keeping control transfer instructions out of the pipeline in architectures without condition codes 

      Cortadella, Jordi; Llaberia Griñó, José M.; González Colás, Antonio María (1987-05)
      Report de recerca
      Accés obert
      The execution of branch instructions involves a loss of performance in pipelined processors. In this paper we present a mechanism for executing this kind of instruction with a zero delay. This mechanism has been proposed ...

    • Shared queues in buffered multistage interconnection networks 

      Domingo Pascual, Jordi; Labarta Mancho, Jesús José; Casals, Olga; Llaberia Griñó, José M.; Valero Cortés, Mateo (1988-01)
      Report de recerca
      Accés obert
      This paper analyses the behaviour of a normal buffered delta network and as a result proposes the use of a shared queue instead of the two queues of the usual switching elements. The performance of the networks with ...

    • FIMSIM: A fault injection infrastructure for microarchitectural simulators 

      Yalcin, Gulay; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2011)
      Report de recerca
      Accés obert
      Fault injection is a widely used approach for experiment-based dependability evaluation in which faults can be injected to the hardware, to the simulator or to the software. Simulation based fault injection is more appealing ...

    • Scalability of parallel video decoding on heterogeneous manycore architectures 

      Álvarez Mesa, Mauricio; Cabarcas Jaramillo, Felipe; Ramírez Bellido, Alejandro; Meenderinck, Cor; Juurlink, Ben; Valero Cortés, Mateo (2011)
      Report de recerca
      Accés obert
      This paper presents an analysis of the scalability of the parallel video decoding on heterogeneous many core architectures. As benchmark, we use a highly parallel H.264/AVC video decoder that generates a large number of ...

    • Circuit design of a dual-versioning L1 data cache for optimistic concurrency 

      Seyedi, Azam; Armejach, Adrià; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Hur, Ibrahim; Valero Cortés, Mateo (2011)
      Report de recerca
      Accés obert
      This paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this new cache architecture, each dvSRAM cell ...

    • Architecture for object-oriented programming model 

      Markovic, Nikola; González, Rubén; Unsal, Osman Sabri; Valero Cortés, Mateo; Cristal Kestelman, Adrián (2009)
      Report de recerca
      Accés obert
      Current mainstream architectures have ISAs that are not able to maintain all the information provided by the application programmer using a high level programming language. Typically, the information that is lost in compiling ...

    • BSLD threshold driven parallel job scheduling for energy efficient HPC centers 

      Etinski, Maja; Corbalán González, Julita; Labarta Mancho, Jesús José; Valero Cortés, Mateo (2009)
      Report de recerca
      Accés obert
      Recently, power awareness in high performance computing (HPC) community has increased significantly. While CPU power reduction of HPC applications using Dynamic Voltage Frequency Scaling (DVFS) has been explored thoroughly, ...

    • Simulating whole supercomputer applications 

      Gonzalez, Juan; Casas, Marc; Moretó Planas, Miquel; Giménez, Judit; Labarta Mancho, Jesús José; Valero Cortés, Mateo (2009)
      Report de recerca
      Accés obert
      Architecture simulation tools are extremely useful not only to predict the performance of future system designs, but also to analyze and improve the performance of software running on well know architectures. However, since ...

    • Overlapping communication and computation by using a hybrid MPI/SMPSs approach 

      Marjanovic, Vladimir; Pérez, Josep M.; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (2009)
      Report de recerca
      Accés obert
      Communication overhead is one of the dominant factors that affect performance in high-performance computing systems. To reduce the negative impact of communication, programmers overlap communication and computation by using ...

    • The MPsim simulation tool 

      Acosta Ojeda, Carmelo Alexis; Cazorla, Francisco; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2009)
      Report de recerca
      Accés obert
      In order to evaluate novel ideas, computer architects require simulation tools which model a target architecture. According to the specific accuracy requirements we find very specific simulators, which model a single ...

    • Maximizing multithreaded multicore architectures through thread migrations 

      Acosta Ojeda, Carmelo Alexis; Cazorla Almeida, Francisco Javier; Santana Jaria, Oliverio J.; Falcón Samper, Ayose Jesús; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2009)
      Report de recerca
      Accés obert
      Heterogeneity in general-purpose workloads often end up in non optimal per-thread hardware resource usage. The current trend towards multicore architectures, containing several multithreaded cores, increases the need of a ...

    • A novel architecture for large windows processors 

      González, Isidro; Galluzzi, Marco; Veidenbaum, Alex; Ramírez, Marco Antonio; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2007-11)
      Report de recerca
      Accés obert
      Several processor architectures with large instruction windows have been proposed. They improve performance by maintaining hundreds of instructions in flight to increase the level of instruction parallelism (ILP). Such ...