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MetH: A family of high-resolution and variable-shape image challenges
(2019-11-20)
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High-resolution and variable-shape images have not yet been properly addressed by the AI community. The approach of down-sampling data often used with convolutional neural networks is sub-optimal for many tasks, and has ...
The Complexity of pure Nash equilibria in weighted Max-Congestion Games
(Universitat Politècnica de Catalunya. Departament de Llenguatges i Sistemes Informàtics, 2008-03-04)
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We study Network Max-Congestion Games (NMC games,
for short), a class of network games where each player tries to minimize
the most congested edge along the path he uses as strategy. We focus
our study on the complexity ...
WormBench: technical report
(2008-08)
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Transactional Memory (TM) is a promising new technology that makes it possible to ease writing multi-threaded applications. Many different TM implementations exist, unfortunately most of those TM systems are currently ...
FIMSIM: A fault injection infrastructure for microarchitectural simulators
(2011)
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Fault injection is a widely used approach for experiment-based dependability evaluation in which faults can be injected to the hardware, to the simulator or to the software. Simulation based fault injection is more appealing ...
Architectural support for real-time task scheduling in SMT processors
(2005)
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In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. ...
A novel architecture for large windows processors
(2007-11)
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Several processor architectures with large instruction windows have been proposed. They improve performance by maintaining hundreds of instructions in flight to increase the level of instruction parallelism (ILP). Such ...
Systolic implementation for deconvolution iterative algorithm
(1985)
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Systolic architectures implement regular algorithms in hardware, in order to obtain high computational throughput. In this paper we provide a modular architecture for a deconvolution iterative algorithm. The basic module ...
Source code transformations for efficient SIMD code generation
(2012-01)
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Despite the effort inverted the last years in commercial compilers to generate efficient SIMD instructions based code sequences from conventional sequential programs, the small numbers of compilers that can automatically ...
The MS-processor's register file timing and power evaluation
(2008-09)
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Power evaluation is an important issue in new proposal chip level architectures due to the big amount of power is dissipated as head and chips have limited head dissipation capacity. The evaluation shown in this technical ...
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
(2011)
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This paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this new cache architecture, each dvSRAM cell ...