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dc.contributor.authorMorad, Tomer Y.
dc.contributor.authorWeiser, Uri C.
dc.contributor.authorKolodny, Avinoam
dc.contributor.authorValero Cortés, Mateo
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2015-06-26T14:24:22Z
dc.date.created2006-01
dc.date.issued2006-01
dc.identifier.citationMorad, T. [et al.]. Performance power efficiency and scalabity of asymmetric chip multiprocessors. "Computer architecture letters", Gener 2006, vol. 5, núm. 1, p. 14-17.
dc.identifier.urihttp://hdl.handle.net/2117/28438
dc.description.abstractThis paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to achieve the highest performance for a given power budget. ACCMPs execute serial phases of multithreaded programs on large high-performance cores whereas parallel phases are executed on a mix of large and many small simple cores. Theoretical analysis reveals a performance upper bound for symmetric multiprocessors, which is surpassed by asymmetric configurations at certain power ranges. Our emulations show that asymmetric multiprocessors can reduce power consumption by more than two thirds with similar performance compared to symmetric multiprocessors
dc.format.extent4 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshMultiprocessors
dc.subject.lcshParallel programming (Computer science)
dc.subject.otherMicroprocessor chips
dc.subject.otherMulti-threading
dc.subject.otherMultiprocessing systems
dc.subject.otherParallel processing
dc.titlePerformance power efficiency and scalabity of asymmetric chip multiprocessors
dc.typeArticle
dc.subject.lemacMultiprocessadors
dc.subject.lemacProgramació en paral·lel (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/L-CA.2006.6
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1650136
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac654913
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorMorad, T.; Weiser, U.; Kolodny, A.; Valero, M.; Ayguade, E.
local.citation.publicationNameComputer architecture letters
local.citation.volume5
local.citation.number1
local.citation.startingPage14
local.citation.endingPage17


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Attribution-NonCommercial-NoDerivs 3.0 Spain
Except where otherwise noted, content on this work is licensed under a Creative Commons license : Attribution-NonCommercial-NoDerivs 3.0 Spain