Performance power efficiency and scalabity of asymmetric chip multiprocessors
Rights accessRestricted access - publisher's policy
This paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to achieve the highest performance for a given power budget. ACCMPs execute serial phases of multithreaded programs on large high-performance cores whereas parallel phases are executed on a mix of large and many small simple cores. Theoretical analysis reveals a performance upper bound for symmetric multiprocessors, which is surpassed by asymmetric configurations at certain power ranges. Our emulations show that asymmetric multiprocessors can reduce power consumption by more than two thirds with similar performance compared to symmetric multiprocessors
CitationMorad, T. [et al.]. Performance power efficiency and scalabity of asymmetric chip multiprocessors. "Computer architecture letters", Gener 2006, vol. 5, núm. 1, p. 14-17.
|Performance, Power Efficiency and Scalability.pdf||Performance, Power Efficiency and Scalability||324,1Kb||Restricted access|