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dc.contributor.authorBalart, J
dc.contributor.authorGonzález Tallada, Marc
dc.contributor.authorMartorell Bofill, Xavier
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorSura, Z
dc.contributor.authorChen, T
dc.contributor.authorZhang, T
dc.contributor.authorO'Brien, Kevin
dc.contributor.authorO'Brien, Kathryn
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2015-06-23T17:22:25Z
dc.date.created2008-10
dc.date.issued2008-10
dc.identifier.citationBalart, J. [et al.]. A novel asynchronous software cache implementation for the Cell-BE processor. "Lecture notes in computer science", Octubre 2008, vol. 5234, núm. 1, p. 125-140.
dc.identifier.issn0302-9743
dc.identifier.urihttp://hdl.handle.net/2117/28386
dc.description.abstractThis paper describes the implementation of a runtime library for asynchronous communication in the Cell BE processor. The runtime library implementation provides with several services that allow the compiler to generate code, maximizing the chances for overlapping communication and computation. The library implementation is organized as a Software Cache and the main services correspond to mechanisms for data look up, data placement and replacement, data write back, memory synchronization and address translation. The implementation guarantees that all those services can be totally uncoupled when dealing with memory references. Therefore this provides opportunities to the compiler to organize the generated code in order to overlap as much as possible computation with communication. The paper also describes the necessary mechanism to overlap the communication related to write back operations with actual computation. The paper includes the description of the compiler basic algorithms and optimizations for code generation. The system is evaluated measuring bandwidth and global updates ratios, with two benchmarks from the HPCC benchmark suite: Stream and Random Access.
dc.format.extent16 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subject.lcshParallel programming (Computer science)
dc.subject.lcshMicroprocessors -- Programming
dc.titleA novel asynchronous software cache implementation for the Cell-BE processor
dc.typeArticle
dc.subject.lemacProgramació en paral·lel (Informàtica)
dc.subject.lemacMicroprocessadors -- Programació
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1007/978-3-540-85261-2_9
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://link.springer.com/chapter/10.1007%2F978-3-540-85261-2_9
dc.rights.accessRestricted access - publisher's policy
drac.iddocument681235
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
upcommons.citation.authorBalart, J.; Gonzalez, M.; Martorell, X.; Ayguade, E.; Sura, Z.; Chen, T.; Zhang, T.; O'Brien, K.; O'Brien, K.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameLecture notes in computer science
upcommons.citation.volume5234
upcommons.citation.number1
upcommons.citation.startingPage125
upcommons.citation.endingPage140


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