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Hardware-software coherence protocol for the coexistence of caches and local memories
dc.contributor.author | Álvarez Martí, Lluc |
dc.contributor.author | Vilanova, Lluís |
dc.contributor.author | González Tallada, Marc |
dc.contributor.author | Martorell Bofill, Xavier |
dc.contributor.author | Navarro, Nacho |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2015-06-15T07:44:25Z |
dc.date.available | 2015-06-15T07:44:25Z |
dc.date.created | 2015-01-01 |
dc.date.issued | 2015-01-01 |
dc.identifier.citation | Álvarez, L. [et al.]. Hardware-software coherence protocol for the coexistence of caches and local memories. "IEEE transactions on computers", 01 Gener 2015, vol. 64, núm. 1, p. 152-165. |
dc.identifier.issn | 0018-9340 |
dc.identifier.uri | http://hdl.handle.net/2117/28300 |
dc.description.abstract | Cache coherence protocols limit the scalability of multicore and manycore architectures and are responsible for an important amount of the power consumed in the chip. A good way to alleviate these problems is to introduce a local memory alongside the cache hierarchy, forming a hybrid memory system. Local memories are more power-efficient than caches and do not generate coherence traffic, but they suffer from poor programmability. When non-predictable memory access patterns are found, compilers do not succeed in generating code because of the incoherence between the two storages. This paper proposes a coherence protocol for hybrid memory systems that allows the compiler to generate code even in the presence of memory aliasing problems. Coherence is ensured by a software/hardware co-design where the compiler identifies potentially incoherent memory accesses and the hardware diverts them to the correct copy of the data. The coherence protocol introduces overheads of 0.26% in execution time and of 2.03% in energy consumption to enable the usage of the hybrid memory system, which outperforms cache-based systems by an speedup of 38% and an energy reduction of 27%. |
dc.format.extent | 14 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Cache memory |
dc.subject.lcsh | Compilers (Computer programs) |
dc.subject.other | Coherence protocol |
dc.subject.other | Lcal memories |
dc.subject.other | Scratchpad memories |
dc.subject.other | Hybrid memory system |
dc.subject.other | Architecture |
dc.subject.other | Performance |
dc.subject.other | Efficient |
dc.subject.other | Systems |
dc.title | Hardware-software coherence protocol for the coexistence of caches and local memories |
dc.type | Article |
dc.subject.lemac | Memòria cau |
dc.subject.lemac | Compiladors (Programes d'ordinador) |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/TC.2013.194 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6616543 |
dc.rights.access | Open Access |
local.identifier.drac | 14581317 |
dc.description.version | Postprint (author’s final draft) |
local.citation.author | Álvarez, L.; Vilanova, L.; Gonzalez, M.; Martorell, X.; Navarro, N.; Ayguade, E. |
local.citation.publicationName | IEEE transactions on computers |
local.citation.volume | 64 |
local.citation.number | 1 |
local.citation.startingPage | 152 |
local.citation.endingPage | 165 |
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