Improving security in cache memory by power efficient scrambling technique
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The last decade has recorded an increase in security protocols for integrated circuits and memory systems, because of device specific attacks such as side-channel monitoring and cold boot and also because sensitive information is stored in such devices. The scope of this study is to propose new security measures which can be applied in memory systems, in order to make the stored data unusable, if retrieved successfully by any type of attack. The security technique uses interleaved scrambling vectors to scramble the data retained in a memory system and employs several dissemination rules. The proposed technique is investigated and assessed from several perspectives, such as power consumption, time performance and area overhead.
CitacióNeagu, M.; Miclea, L.; Manich, S. Improving security in cache memory by power efficient scrambling technique. "IET computers and digital techniques", 08 Abril 2015, p. 1-10.
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