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AMMC: advance multi-core memory controller
dc.contributor.author | Hussain, Tassadaq |
dc.contributor.author | Palomar Pérez, Óscar |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Barcelona Supercomputing Center |
dc.date.accessioned | 2015-05-14T13:07:02Z |
dc.date.available | 2015-05-14T13:07:02Z |
dc.date.created | 2014 |
dc.date.issued | 2014 |
dc.identifier.citation | Hussain, T. [et al.]. AMMC: advance multi-core memory controller. A: International Conference on Field-Programmable Technology. "Proceedings of the 2014 International Conference on Field-Programmable Technology (FPT): Dec. 10-12, 2014: Shanghai, China". Shanghai: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 292-295. |
dc.identifier.isbn | 978-1-4799-6244-0 |
dc.identifier.uri | http://hdl.handle.net/2117/27916 |
dc.description.abstract | In this work, we propose an efficient scheduler and intelligent memory manager known as AMMC (Advanced Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed AMMC system improves performance by managing complex data transfers at run-time and scheduling multi-cores without the intervention of a control processor nor an operating system. AMMC has been coupled with a heterogeneous system that provides both general-purpose cores and application specific accelerators. The AMMC system is implemented and tested on a Xilinx ML505 evaluation FPGA board. The performance of the system is compared with a microprocessor based system that has been integrated with the Xilkernel operating system. Results show that the AMMC based multi-core system consumes 48% less hardware resources, 27.9% less on-chip power and achieves 6.8x of speed-up compared to the MicroBlaze-based multi-core system. |
dc.format.extent | 4 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Sistemes d'informació::Emmagatzematge i recuperació de la informació |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica |
dc.subject.lcsh | Memory management (Computer science) |
dc.subject.lcsh | Field programmable gate arrays |
dc.subject.other | Field programmable gate arrays |
dc.subject.other | Microprocessor chips |
dc.subject.other | Multiprocessing systems |
dc.subject.other | Operating system kernels |
dc.subject.other | Scheduling |
dc.title | AMMC: advance multi-core memory controller |
dc.type | Conference lecture |
dc.subject.lemac | Gestió de memòria (Informàtica) |
dc.subject.lemac | Matrius de portes programables per l'usuari |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/FPT.2014.7082802 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7082802&tag=1 |
dc.rights.access | Open Access |
local.identifier.drac | 15626022 |
dc.description.version | Postprint (author’s final draft) |
local.citation.author | Hussain, T.; Palomar, O.; Unsal, O.; Cristal, A.; Ayguade, E.; Valero, M. |
local.citation.contributor | International Conference on Field-Programmable Technology |
local.citation.pubplace | Shanghai |
local.citation.publicationName | Proceedings of the 2014 International Conference on Field-Programmable Technology (FPT): Dec. 10-12, 2014: Shanghai, China |
local.citation.startingPage | 292 |
local.citation.endingPage | 295 |