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dc.contributor.authorHussain, Tassadaq
dc.contributor.authorHaider, Amna
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2015-05-07T12:11:55Z
dc.date.created2014-10
dc.date.issued2014-10
dc.identifier.citationHussain, T.; Haider, A.; Ayguade, E. PMSS: a programmable memory system and scheduler for complex memory patterns. "Journal of parallel and distributed computing", Octubre 2014, vol. 74, núm. 15, p. 2983-2993.
dc.identifier.issn0743-7315
dc.identifier.urihttp://hdl.handle.net/2117/27820
dc.description.abstractHPC industry demands more computing units on FPGAs, to enhance the performance by using task/data parallelism. FPGAs can provide its ultimate performance on certain kernels by customizing the hardware for the applications. However, applications are getting more complex, with multiple kernels and complex data arrangements, generating overhead while scheduling/managing system resources. Due to this reason all classes of multi threaded machines–minicomputer to supercomputer–require to have efficient hardware scheduler and memory manager that improves the effective bandwidth and latency of the DRAM main memory. This architecture could be a very competitive choice for supercomputing systems that meets the demand of parallelism for HPC benchmarks. In this article, we proposed a Programmable Memory System and Scheduler (PMSS), which provides high speed complex data access pattern to the multi threaded architecture. This proposed PMSS system is implemented and tested on a Xilinx ML505 evaluation FPGA board. The performance of the system is compared with a microprocessor based system that has been integrated with the Xilkernel operating system. Results show that the modified PMSS based multi-accelerator system consumes 50% less hardware resources, 32% less on-chip power and achieves approximately a 19x speedup compared to the MicroBlaze based system.
dc.format.extent11 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subjectÀrees temàtiques de la UPC::Informàtica::Sistemes d'informació::Emmagatzematge i recuperació de la informació
dc.subject.lcshComputer storage devices
dc.subject.lcshParallel programming (Computer science)
dc.subject.otherHPC
dc.subject.otherDRAM
dc.subject.otherXilkernel
dc.subject.otherFPGA
dc.titlePMSS: a programmable memory system and scheduler for complex memory patterns
dc.typeArticle
dc.subject.lemacOrdinadors -- Dispositius de memòria
dc.subject.lemacProgramació en paral·lel (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1016/j.jpdc.2014.06.005
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://www.sciencedirect.com/science/article/pii/S0743731514001075
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac15625235
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorHussain, T.; Haider, A.; Ayguade, E.
local.citation.publicationNameJournal of parallel and distributed computing
local.citation.volume74
local.citation.number15
local.citation.startingPage2983
local.citation.endingPage2993


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Attribution-NonCommercial-NoDerivs 3.0 Spain
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