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dc.contributor.authorSlijepcevic, Mladen
dc.contributor.authorKosmidis, Leonidas
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorQuiñones, Eduardo
dc.contributor.authorCazorla, Francisco J.
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2015-04-22T14:02:44Z
dc.date.created2014-11-01
dc.date.issued2014-11-01
dc.identifier.citationSlijepcevic, M. [et al.]. Timing verification of fault-tolerant chips for safety-critical applications in harsh environments. "IEEE micro", 01 Novembre 2014, vol. 34, núm. 6, p. 7-18.
dc.identifier.issn0272-1732
dc.identifier.urihttp://hdl.handle.net/2117/27520
dc.description.abstractCritical real-time embedded systems feature complex safety-related, performance-demanding functionality. High-performance hardware and software can provide such functionality, but the use of aggressive technologies and architectures challenges time predictability and reliability. The authors propose a new approach to obtain trustworthy worst-case execution time estimates for safety-critical applications running on high-performance faulty hardware by using both timing-analysis techniques and minor hardware modifications.
dc.format.extent12 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshFault-tolerant computing
dc.subject.lcshEmbedded computer systems
dc.subject.otherSystems
dc.subject.otherCaches
dc.subject.otherEmbedded systems
dc.subject.otherFault tolerant computing
dc.subject.otherFormal verification
dc.subject.otherParallel processing
dc.subject.otherProgram diagnostics
dc.subject.otherSafety-critical software
dc.titleTiming verification of fault-tolerant chips for safety-critical applications in harsh environments
dc.typeArticle
dc.subject.lemacTolerància als errors (Informàtica)
dc.subject.lemacSistemes incrustats (Informàtica)
dc.identifier.doi10.1109/MM.2014.59
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6853246
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac15389194
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorSlijepcevic, M.; Kosmidis, L.; Abella, J.; Quiñones, E.; Cazorla, F.J.
local.citation.publicationNameIEEE micro
local.citation.volume34
local.citation.number6
local.citation.startingPage7
local.citation.endingPage18


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