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Timing verification of fault-tolerant chips for safety-critical applications in harsh environments
dc.contributor.author | Slijepcevic, Mladen |
dc.contributor.author | Kosmidis, Leonidas |
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | Quiñones, Eduardo |
dc.contributor.author | Cazorla, Francisco J. |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2015-04-22T14:02:44Z |
dc.date.created | 2014-11-01 |
dc.date.issued | 2014-11-01 |
dc.identifier.citation | Slijepcevic, M. [et al.]. Timing verification of fault-tolerant chips for safety-critical applications in harsh environments. "IEEE micro", 01 Novembre 2014, vol. 34, núm. 6, p. 7-18. |
dc.identifier.issn | 0272-1732 |
dc.identifier.uri | http://hdl.handle.net/2117/27520 |
dc.description.abstract | Critical real-time embedded systems feature complex safety-related, performance-demanding functionality. High-performance hardware and software can provide such functionality, but the use of aggressive technologies and architectures challenges time predictability and reliability. The authors propose a new approach to obtain trustworthy worst-case execution time estimates for safety-critical applications running on high-performance faulty hardware by using both timing-analysis techniques and minor hardware modifications. |
dc.format.extent | 12 p. |
dc.language.iso | eng |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
dc.subject.lcsh | Fault-tolerant computing |
dc.subject.lcsh | Embedded computer systems |
dc.subject.other | Systems |
dc.subject.other | Caches |
dc.subject.other | Embedded systems |
dc.subject.other | Fault tolerant computing |
dc.subject.other | Formal verification |
dc.subject.other | Parallel processing |
dc.subject.other | Program diagnostics |
dc.subject.other | Safety-critical software |
dc.title | Timing verification of fault-tolerant chips for safety-critical applications in harsh environments |
dc.type | Article |
dc.subject.lemac | Tolerància als errors (Informàtica) |
dc.subject.lemac | Sistemes incrustats (Informàtica) |
dc.identifier.doi | 10.1109/MM.2014.59 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6853246 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 15389194 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Slijepcevic, M.; Kosmidis, L.; Abella, J.; Quiñones, E.; Cazorla, F.J. |
local.citation.publicationName | IEEE micro |
local.citation.volume | 34 |
local.citation.number | 6 |
local.citation.startingPage | 7 |
local.citation.endingPage | 18 |
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