dc.contributor.author | Rana, Manish |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2015-04-17T17:47:50Z |
dc.date.created | 2014 |
dc.date.issued | 2014 |
dc.identifier.citation | Rana, M.; Canal, R. REEM: failure/non-failure region estimation method for SRAM yield analysis. A: IEEE International Conference on Computer Design. "2014 32nd IEEE International Conference on Computer Design (ICCD): October 19-22, 2014: Seoul, Korea". Seul: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 36-41. |
dc.identifier.isbn | 978-1-4799-6492-5 |
dc.identifier.uri | http://hdl.handle.net/2117/27445 |
dc.description.abstract | The big challenge that we face today for designing resilient memories is the huge number of simulations needed to arrive at a good estimate of memory's yield. A lot of work has come up recently focusing on the reduction of these simulations. The majority of these methods have focused on using different Markov Chain Monte Carlo (MCMC) methods, most notably Importance Sampling. SRAMs, though, have an interesting property of failure monotonicity which implies that given a known failure point in SRAM's parameter space all points with larger variations will also be failure points. Our work REEM (Region Estimation by Exploiting Monotonicity), thus, focuses on exploiting the SRAM's failure monotonicity property for faster estimation of the Failure/Non-Failure regions. The usual MCMC methods can then be used without needing actual spice simulations. Our results show that using our method we can achieve an overall 10x reduction in simulations compared to traditional Importance Sampling methods. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Sistemes d'informació::Emmagatzematge i recuperació de la informació |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Memory management (Computer science) |
dc.subject.lcsh | Integrated circuits |
dc.subject.other | Importance sampling |
dc.subject.other | Markov processes |
dc.subject.other | Static random access storage |
dc.subject.other | 10x reductions |
dc.subject.other | Estimation methods |
dc.subject.other | Importance sampling method |
dc.subject.other | Markov chain Monte Carlo method |
dc.subject.other | Monotonicity property |
dc.subject.other | Parameter spaces |
dc.subject.other | SPICE simulations |
dc.subject.other | Yield analysis |
dc.title | REEM: failure/non-failure region estimation method for SRAM yield analysis |
dc.type | Conference report |
dc.subject.lemac | Gestió de memòria (Informàtica) |
dc.subject.lemac | Circuits integrats |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/ICCD.2014.6974659 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6974659 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 15415877 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Rana, M.; Canal, R. |
local.citation.contributor | IEEE International Conference on Computer Design |
local.citation.pubplace | Seul |
local.citation.publicationName | 2014 32nd IEEE International Conference on Computer Design (ICCD): October 19-22, 2014: Seoul, Korea |
local.citation.startingPage | 36 |
local.citation.endingPage | 41 |