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dc.contributor.authorHussain, Tassadaq
dc.contributor.authorSönmez, Nehir
dc.contributor.authorPalomar Pérez, Óscar
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorValero Cortés, Mateo
dc.contributor.authorGursal, Shakaib A.
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.identifier.citationHussain, T. [et al.]. PAMS: pattern aware memory system for embedded systems. A: International Conference on ReConFigurable Computing and FPGAs. "2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig14): Cancun, Mexico: December 8-10, 2014". Cancun: Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 1-7.
dc.description.abstractIn this paper, we propose a hardware mechanism for embedded multi-core memory system called Pattern Aware Memory System (PAMS). The PAMS supports static and dynamic data structures using descriptors and specialized memory and reduces area, cost, energy consumption and hit latency. When compared with a Baseline Memory System, the PAMS consumes between 3 and 9 times and 1.13 and 2.66 times less program memory for static and dynamic data structures respectively. The benchmarking applications (having static and dynamic data structures) results show that PAMS consumes 20% less hardware resources, 32% less on chip power and achieves a maximum speedup of 52x and 2.9x for static and dynamic data structures respectively. The results show that the PAMS multi-core system transfers data structures up to 4.65x faster than the MicroBlaze baseline system.
dc.description.sponsorshipThe research leading to these results has received funding from the European Research Council under the European Unions 7th FP (FP/2007-2013) / ERC GA n. 321253. It has been partially funded by the Spanish Government (TIN2014-34557). The authors would like to thank the Barcelona Supercom- puting Center and the Unal Center of Education Research and Development (UCERD) for their support.
dc.format.extent7 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Hardware
dc.subjectÀrees temàtiques de la UPC::Informàtica::Sistemes d'informació::Emmagatzematge i recuperació de la informació
dc.subject.lcshMemory management (Computer science)
dc.subject.otherData structures
dc.subject.otherEmbedded systems
dc.subject.otherMultiprocessing systems
dc.subject.otherStorage management
dc.titlePAMS: pattern aware memory system for embedded systems
dc.typeConference report
dc.subject.lemacGestió de memòria (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
local.citation.authorHussain, T.; Sonmez, N.; Palomar, O.; Unsal, O.; Cristal, A.; Ayguade, E.; Valero, M.; Gursal, S.
local.citation.contributorInternational Conference on ReConFigurable Computing and FPGAs
local.citation.publicationName2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig14): Cancun, Mexico: December 8-10, 2014

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