PAMS: pattern aware memory system for embedded systems
Tipo de documentoTexto en actas de congreso
Fecha de publicación2015
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condiciones de accesoAcceso abierto
Proyecto de la Comisión EuropeaROMOL - Riding on Moore's Law (EC-FP7-321253)
In this paper, we propose a hardware mechanism for embedded multi-core memory system called Pattern Aware Memory System (PAMS). The PAMS supports static and dynamic data structures using descriptors and specialized memory and reduces area, cost, energy consumption and hit latency. When compared with a Baseline Memory System, the PAMS consumes between 3 and 9 times and 1.13 and 2.66 times less program memory for static and dynamic data structures respectively. The benchmarking applications (having static and dynamic data structures) results show that PAMS consumes 20% less hardware resources, 32% less on chip power and achieves a maximum speedup of 52x and 2.9x for static and dynamic data structures respectively. The results show that the PAMS multi-core system transfers data structures up to 4.65x faster than the MicroBlaze baseline system.
CitaciónHussain, T. [et al.]. PAMS: pattern aware memory system for embedded systems. A: International Conference on ReConFigurable Computing and FPGAs. "2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig14): Cancun, Mexico: December 8-10, 2014". Cancun: Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 1-7.
Versión del editorhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7032544