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MAPC: memory access pattern based controller
dc.contributor.author | Hussain, Tassadaq |
dc.contributor.author | Palomar Pérez, Óscar |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2015-04-17T17:40:49Z |
dc.date.created | 2014 |
dc.date.issued | 2014 |
dc.identifier.citation | Hussain, T. [et al.]. MAPC: memory access pattern based controller. A: International Conference on Field-Programmable Logic and Applications. "24th International Conference on Field Programmable Logic and Applications (FPL): Munich, Germany, 2-4 September 2014". Munich: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 1-4. |
dc.identifier.isbn | 978-1-4799-3362-4 |
dc.identifier.uri | http://hdl.handle.net/2117/27442 |
dc.description.abstract | Traditionally, system designers have attempted to improve system performance by scheduling the processing cores and by exploring different memory system configurations and there is comparatively less work done scheduling the accesses at the memory system level and exploring data accesses on the memory systems. In this paper, we propose a memory access pattern based controller (MAPC). MAPC organizes data accesses in descriptors, prioritizes them with respect to the number and size of transfer requests. When compared to the baseline multicore system, the MAPC based system achieves between 2.41× to 5.34× of speedup for different applications, consumes 28% less hardware resources and 13% less dynamic power. |
dc.format.extent | 4 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Sistemes d'informació::Emmagatzematge i recuperació de la informació |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació |
dc.subject.lcsh | Memory management (Computer science) |
dc.subject.lcsh | Field programmable gate arrays |
dc.subject.other | Programmable controllers |
dc.subject.other | Random-access storage |
dc.subject.other | Bandwidth |
dc.subject.other | Data transfer |
dc.subject.other | Hardware |
dc.subject.other | Memory management |
dc.subject.other | Multicore processing |
dc.subject.other | SDRAM |
dc.subject.other | Scheduling |
dc.subject.other | MAPC |
dc.subject.other | Access pattern descriptors |
dc.subject.other | Data transfers |
dc.subject.other | Memory access pattern based controller |
dc.title | MAPC: memory access pattern based controller |
dc.type | Conference report |
dc.subject.lemac | Gestió de memòria (Informàtica) |
dc.subject.lemac | Matrius de portes programables per l'usuari |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/FPL.2014.6927397 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6927397 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 15430801 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Hussain, T.; Palomar, O.; Unsal, O.; Cristal, A.; Ayguade, E.; Valero, M. |
local.citation.contributor | International Conference on Field-Programmable Logic and Applications |
local.citation.pubplace | Munich |
local.citation.publicationName | 24th International Conference on Field Programmable Logic and Applications (FPL): Munich, Germany, 2-4 September 2014 |
local.citation.startingPage | 1 |
local.citation.endingPage | 4 |