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VPPET: virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms

dc.contributor.authorRethinagiri, Santhosh Kumar
dc.contributor.authorPalomar Pérez, Óscar
dc.contributor.authorArias Moreno, Francisco Javier
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2015-04-17T17:28:41Z
dc.date.created2014
dc.date.issued2014
dc.identifier.citationRethinagiri, S. [et al.]. VPPET: virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms. A: International Workshop on Power and Timing Modeling, Optimization and Simulation. "14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2014): Palma de Mallorca, Spain: 29 September-1 October 2014". Palma de Mallorca: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 6951910-1-6951910-8.
dc.identifier.isbn9781479954131
dc.identifier.urihttp://hdl.handle.net/2117/27440
dc.description.abstractUsing low-power symmetric multi-cores on FPGAs are becoming ubiquitous in embedded computing. This is due to the emergence of power and energy as key design metrics, as important as performance. This leads to the requirement of powerful and reliable tools, which will be used for the Design Space Exploration (DSE) based on power and energy at an early stage of the design flow. In this paper, we propose a simulation based virtual platform power and energy estimation tool for heterogeneous Multiprocessor System-on-Chip (MPSoC) based platforms. There are two steps involved in this tool development. The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for different parts of the system. This is a one-time activity. In the second step, a simulation based virtual platform framework is developed to accurately grab the activities used in the related power models generated in the first step. The combination of the two steps leads to a hybrid power estimation, which gives a better trade-off between accuracy and speed. The proposed tool is automated and also scalable for exploring complex embedded multi-core architectures. The efficiency of the proposed tool is validated through multi-cores/processors designed around the FPGAs and extended to accommodate futuristic multi-processors/cores for a reliable energy based DSE. The obtained power/energy estimation results provide less than 4% of error for single core processor, 8% for dual-core processor and 9% for heterogeneous MPSoC based systems when compared to real board measurements.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Hardware
dc.subjectÀrees temàtiques de la UPC::Informàtica::Informàtica teòrica::Algorísmica i teoria de la complexitat
dc.subject.lcshField programmable gate arrays
dc.subject.lcshMultiprocessors
dc.subject.otherApplication specific integrated circuits
dc.subject.otherComputer architecture
dc.subject.otherComputer simulation
dc.subject.otherDesign
dc.subject.otherEconomic and social effects
dc.subject.otherEmbedded systems
dc.subject.otherMicroprocessor chips
dc.subject.otherMultiprocessing systems
dc.subject.otherSystem-on-chip
dc.subject.otherUbiquitous computing
dc.titleVPPET: virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms
dc.typeConference report
dc.subject.lemacMatrius de portes programables per l'usuari
dc.subject.lemacMultiprocessadors
dc.identifier.doi10.1109/PATMOS.2014.6951910
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6951910
dc.rights.accessRestricted access - publisher's policy
drac.iddocument15415930
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
upcommons.citation.authorRethinagiri, S.; Palomar, O.; Arias, F.J.; Unsal, O.; Cristal, A.
upcommons.citation.contributorInternational Workshop on Power and Timing Modeling, Optimization and Simulation
upcommons.citation.pubplacePalma de Mallorca
upcommons.citation.publishedtrue
upcommons.citation.publicationName14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2014): Palma de Mallorca, Spain: 29 September-1 October 2014
upcommons.citation.startingPage6951910-1
upcommons.citation.endingPage6951910-8


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