VPPET: virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms

Rethinagiri, Santhosh Kumar; Palomar Pérez, Óscar; Arias Moreno, Francisco Javier; Unsal, Osman Sabri; Cristal Kestelman, Adrián

doi:10.1109/PATMOS.2014.6951910

dc.contributor.author	Rethinagiri, Santhosh Kumar
dc.contributor.author	Palomar Pérez, Óscar
dc.contributor.author	Arias Moreno, Francisco Javier
dc.contributor.author	Unsal, Osman Sabri
dc.contributor.author	Cristal Kestelman, Adrián
dc.contributor.other	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned	2015-04-17T17:28:41Z
dc.date.created	2014
dc.date.issued	2014
dc.identifier.citation	Rethinagiri, S. [et al.]. VPPET: virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms. A: International Workshop on Power and Timing Modeling, Optimization and Simulation. "14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2014): Palma de Mallorca, Spain: 29 September-1 October 2014". Palma de Mallorca: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 6951910-1-6951910-8.
dc.identifier.isbn	9781479954131
dc.identifier.uri	http://hdl.handle.net/2117/27440
dc.description.abstract	Using low-power symmetric multi-cores on FPGAs are becoming ubiquitous in embedded computing. This is due to the emergence of power and energy as key design metrics, as important as performance. This leads to the requirement of powerful and reliable tools, which will be used for the Design Space Exploration (DSE) based on power and energy at an early stage of the design flow. In this paper, we propose a simulation based virtual platform power and energy estimation tool for heterogeneous Multiprocessor System-on-Chip (MPSoC) based platforms. There are two steps involved in this tool development. The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for different parts of the system. This is a one-time activity. In the second step, a simulation based virtual platform framework is developed to accurately grab the activities used in the related power models generated in the first step. The combination of the two steps leads to a hybrid power estimation, which gives a better trade-off between accuracy and speed. The proposed tool is automated and also scalable for exploring complex embedded multi-core architectures. The efficiency of the proposed tool is validated through multi-cores/processors designed around the FPGAs and extended to accommodate futuristic multi-processors/cores for a reliable energy based DSE. The obtained power/energy estimation results provide less than 4% of error for single core processor, 8% for dual-core processor and 9% for heterogeneous MPSoC based systems when compared to real board measurements.
dc.language.iso	eng
dc.publisher	Institute of Electrical and Electronics Engineers (IEEE)
dc.rights	Attribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subject	Àrees temàtiques de la UPC::Informàtica::Hardware
dc.subject	Àrees temàtiques de la UPC::Informàtica::Informàtica teòrica::Algorísmica i teoria de la complexitat
dc.subject.lcsh	Field programmable gate arrays
dc.subject.lcsh	Multiprocessors
dc.subject.other	Application specific integrated circuits
dc.subject.other	Computer architecture
dc.subject.other	Computer simulation
dc.subject.other	Design
dc.subject.other	Economic and social effects
dc.subject.other	Embedded systems
dc.subject.other	Microprocessor chips
dc.subject.other	Multiprocessing systems
dc.subject.other	System-on-chip
dc.subject.other	Ubiquitous computing
dc.title	VPPET: virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms
dc.type	Conference report
dc.subject.lemac	Matrius de portes programables per l'usuari
dc.subject.lemac	Multiprocessadors
dc.identifier.doi	10.1109/PATMOS.2014.6951910
dc.description.peerreviewed	Peer Reviewed
dc.relation.publisherversion	http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6951910
dc.rights.access	Restricted access - publisher's policy
drac.iddocument	15415930
dc.description.version	Postprint (published version)
dc.date.lift	10000-01-01
upcommons.citation.author	Rethinagiri, S.; Palomar, O.; Arias, F.J.; Unsal, O.; Cristal, A.
upcommons.citation.contributor	International Workshop on Power and Timing Modeling, Optimization and Simulation
upcommons.citation.pubplace	Palma de Mallorca
upcommons.citation.published	true
upcommons.citation.publicationName	14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2014): Palma de Mallorca, Spain: 29 September-1 October 2014
upcommons.citation.startingPage	6951910-1
upcommons.citation.endingPage	6951910-8