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Leveraging OmpSs to exploit hardware accelerators
dc.contributor.author | Sainz, Florentino |
dc.contributor.author | Mateo Bellido, Sergi |
dc.contributor.author | Beltran Querol, Vicenç |
dc.contributor.author | Bosque, José L. |
dc.contributor.author | Martorell Bofill, Xavier |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2015-04-16T17:53:44Z |
dc.date.created | 2014 |
dc.date.issued | 2014 |
dc.identifier.citation | Sainz, F. [et al.]. Leveraging OmpSs to exploit hardware accelerators. A: International Symposium on Computer Architecture and High Performance Computing. "IEEE 26th International Symposium on Computer Architecture and High Performance Computing: 22–24 October 2014: Paris, France: proceedings". París: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 112-119. |
dc.identifier.isbn | 978-1-4799-6904-3 |
dc.identifier.uri | http://hdl.handle.net/2117/27402 |
dc.description.abstract | CUDA and OpenCL are the most widely used programming models to exploit hardware accelerators. Both programming models provide a C-based programming language to write accelerator kernels and a host API used to glue the host and kernel parts. Although this model is a clear improvement over a low-level and ad-hoc programming model for each hardware accelerator, it is still too complex and cumbersome for general adoption. For large and complex applications using several accelerators, the main problem becomes the explicit coordination and management of resources required between the host and the hardware accelerators that introduce a new family of issues (scheduling, data transfers, synchronization,...) that the programmer must take into account. In this paper, we propose a simple extension to OmpSs - a data-flow programming model - that dramatically simplifies the integration of accelerated code, in the form of CUDA or OpenCL kernels, into any C, C++ or Fortran application. Our proposal fully replaces the CUDA and OpenCL host APIs with a few pragmas, so we can leverage any kernel written in CUDA C or OpenCL C without any performance impact. Our compiler generates all the boilerplat code while our runtime system takes care of kernels scheduling, data transfers between host and accelerators and synchronizations between host and kernels parts. To evaluate our approach, we have ported several native CUDA and OpenCL applications to OmpSs by replacing all the CUDA or OpenCL API calls by a few number of pragmas. The OmpSs versions of these applications have competitive performance and scalability but with a significantly lower complexity than the original ones. |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Llenguatges de programació::C |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
dc.subject.lcsh | C (Computer program language) |
dc.subject.lcsh | Parallel programming (Computer science) |
dc.subject.other | Accelerator |
dc.subject.other | CUDA |
dc.subject.other | OmpSs |
dc.subject.other | OpenCL |
dc.title | Leveraging OmpSs to exploit hardware accelerators |
dc.type | Conference report |
dc.subject.lemac | C (Llenguatge de programació) |
dc.subject.lemac | Programació en paral·lel (Informàtica) |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/SBAC-PAD.2014.26 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6970654 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 15428326 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Sainz, F.; Mateo, S.; Beltran, V.; Bosque, J.; Martorell, X.; Ayguade, E. |
local.citation.contributor | International Symposium on Computer Architecture and High Performance Computing |
local.citation.pubplace | París |
local.citation.publicationName | IEEE 26th International Symposium on Computer Architecture and High Performance Computing: 22–24 October 2014: Paris, France: proceedings |
local.citation.startingPage | 112 |
local.citation.endingPage | 119 |