MAPC: memory access pattern based controller

Traditionally, system designers have attempted to improve system performance by scheduling the processing cores and by exploring different memory system configurations and there is comparatively less work done scheduling the accesses at the memory system level and exploring data accesses on the memory systems. In this paper, we propose a memory access pattern based controller (MAPC). MAPC organizes data accesses in descriptors, prioritizes them with respect to the number and size of transfer requests. When compared to the baseline multicore system, the MAPC based system achieves between 2.41× to 5.34× of speedup for different applications, consumes 28% less hardware resources and 13% less dynamic power.

CitationHussain, T. [et al.]. MAPC: memory access pattern based controller. A: International Conference on Field Programmable Logic and Applications. "Conference Digest: 24th International Conference on Field Programmable Logic and Applications: Technische Universität München, Germany: September 1-5, 2014". Munich: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 1-4.

URIhttp://hdl.handle.net/2117/27368

DOI10.1109/FPL.2014.6927397

ISBN978-300044645-0

Publisher versionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6927397

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