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dc.contributor.authorCortadella, Jordi
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.date.accessioned2015-04-13T09:20:30Z
dc.date.available2015-04-13T09:20:30Z
dc.date.created2013-11
dc.date.issued2013-11
dc.identifier.citationCortadella, J. Area-optimal transistor folding for 1-D gridded cell design. "IEEE transactions on computer-aided design of integrated circuits and systems", Novembre 2013, vol. 32, núm. 11, p. 1708-1721.
dc.identifier.issn0278-0070
dc.identifier.urihttp://hdl.handle.net/2117/27265
dc.description.abstractThe 1-D design style with gridded design rules is gaining ground for addressing the printability issues in subwavelength photolithography. One of the synthesis problems in cell generation is transistor folding, which consists of breaking large transistors into smaller ones (legs) that can be placed in the active area of the cell. In the 1-D style, diffusion sharing between differently sized transistors is not allowed, thus implying a significant area overhead when active areas with different sizes are required. This paper presents a new formulation of the transistor folding problem in the context of 1-D design style and a mathematical model that delivers area-optimal solutions. The mathematical model can be customized for different variants of the problem, considering flexible transistor sizes and multiple-height cells. An innovative feature of the method is that area optimality can be guaranteed without calculating the actual location of the transistors. The model can also be enhanced to deliver solutions with good routability properties.
dc.format.extent14 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors
dc.subject.lcshTransistors
dc.subject.otherCell generation
dc.subject.otherDesign for manufacturability
dc.subject.otherLinear programming
dc.subject.otherTransistor folding
dc.subject.otherTransistor sizing
dc.titleArea-optimal transistor folding for 1-D gridded cell design
dc.typeArticle
dc.subject.lemacTransistors
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.identifier.doi10.1109/TCAD.2013.2269680
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/6634571
dc.rights.accessOpen Access
local.identifier.drac12909024
dc.description.versionPostprint (author’s final draft)
local.citation.authorCortadella, J.
local.citation.publicationNameIEEE transactions on computer-aided design of integrated circuits and systems
local.citation.volume32
local.citation.number11
local.citation.startingPage1708
local.citation.endingPage1721


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