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dc.contributor.authorUpasani, Gaurang
dc.contributor.authorVera Rivera, Francisco Javier
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationUpasani, G.; Vera, X.; Gonzalez, A. Framework for economical error recovery in embedded cores. A: IEEE International On-Line Testing Symposium. "Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium (IOLTS): 7-9 July 2014, Hotel Cap Roig, Platja d’Aro, Catalunya, Spain". Platja d'Aro: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 146-153.
dc.description.abstractThe vulnerability of the current and future processors towards transient errors caused by particle strikes is expected to increase rapidly because of exponential growth rate of on-chip transistors, the lower voltages and the shrinking feature size. This encourages innovation in the direction of finding new techniques for providing robustness in logic and memories that allow meeting the desired failures in-time (FIT) budget in future chip multiprocessors (CMPs) present in embedded systems. In embedded systems two aspects of robustness, error detection and containment, are of paramount importance. This paper proposes a light-weight and scalable architecture that uses acoustic wave detectors for error detection and contains errors at the core level. We show how selectively applying error containment can reduce the number of detectors required for error containment. We observe that by using 17 detectors we can achieve error containment coverage of 97.8%. © 2014 IEEE.
dc.format.extent8 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subjectÀrees temàtiques de la UPC::Informàtica::Sistemes d'informació::Emmagatzematge i recuperació de la informació
dc.subject.lcshEmbedded computer systems
dc.subject.lcshMemory management (Computer science)
dc.subject.otherBudget control
dc.subject.otherError detection
dc.subject.otherChip multi-processors (CMPs)
dc.subject.otherExponential growth rates
dc.subject.otherLower voltages
dc.subject.otherOn-chip transistors
dc.subject.otherScalable architectures
dc.subject.otherShrinking feature sizes
dc.subject.otherTransient errors
dc.subject.otherWave detectors
dc.subject.otherEmbedded systems
dc.titleFramework for economical error recovery in embedded cores
dc.typeConference report
dc.subject.lemacSistemes incrustats (Informàtica)
dc.subject.lemacGestió de memòria (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
dc.description.versionPostprint (published version)
upcommons.citation.authorUpasani, G.; Vera, X.; Gonzalez, A.
upcommons.citation.contributorIEEE International On-Line Testing Symposium
upcommons.citation.pubplacePlatja d'Aro
upcommons.citation.publicationNameProceedings of the 2014 IEEE 20th International On-Line Testing Symposium (IOLTS): 7-9 July 2014, Hotel Cap Roig, Platja d’Aro, Catalunya, Spain

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